MONTEREY, Calif. " Crosstalk and power are extremely difficult problems to solve, and will require significant changes to the existing chip design flow, according to Li-Pen Yuan, R&D director for extraction and signal integrity at Synopsys. Yuan offered a keynote speech at the Electronic Design Processes (EDP-2004) methodology conference here Monday (April 26).
In his talk, Yuan showed why signal integrity and power analysis are so complicated for EDA tools to solve, and how they change assumptions made throughout the design flow. The problem is particularly severe for chips with multiple supply voltages or power "modes," he noted.
"The future is going to be very noisy," Yuan said. "The problem involves the entire chip and system. To solve the problem in a divide-and-conquer way is going to be very complicated."
Yuan noted that some problems can be solved with incremental changes to existing design systems. These include hot current effects and signal electromigration. Others, like timing, can be solved by making more information available. But some change the fundamentals of existing software systems, such as power in multi-Vdd or multi-mode designs. And some challenge the fundamentals of the design flow, including crosstalk and resistive shielding.
Crosstalk is difficult, Yuan said, because it introduces spatial correlations between signals. "Before, you only had logical correlations, but now you have to look at the physical proximity of routing," he said. To solve the problem, one must consider routing patterns, drive strength, clock domains, and timing windows, driving complexity up exponentially.
Yuan also noted that crosstalk analysis needs to consider the nonlinear behavior of digital circuits, requires models with more attributes, demands additional physical and timing constraints, and calls for a reduction of pessimism. Further, he noted, "crosstalk destroys hierarchy. A lot of assumptions made in the hierarchical flow must be revisited."
No single step or tool can solve crosstalk alone, Yuan noted. A crosstalk-aware design flow must include placement, global routing, and engineering change orders (ECOs). Aggressiveness in prevention and correction must be balanced with timing, power, and area concerns.
Power analysis, Yuan noted, is complicated by power management techniques, which are aimed at reducing dynamic and leakage power. Such techniques may include multiple voltages, clock gating, and "modes" that shut down portions of the chip to conserve power. There's a real need, he said, for multi-mode power analysis.
"Power management doesn't come free," Yuan noted. "The multi-mode control of circuit function worsens gradients of current distribution, leading to inductive noise."
To run power supply noise analysis, Yuan said, changes are needed in library characterization, parasitic extraction, timing analysis, and dynamic analysis. Voltage-dependent timing models are needed to drive voltage-drop dependent timing analysis.
"We must be able to understand the analog behavior of circuits in order to continue the path of digital designs," Yuan noted.
Yuan said, however, that EDA developers and users need to be aware of the "limits of automation." Users will need to contribute design knowledge and interact with tools to make them less pessimistic, he said.
EDP is a small but influential conference for CAD methodology experts. Presentations will be available in May at the conference web site.