AUSTIN, Texas Semiconductor companies are coming face-to-face with a pair of materials challenges daunting enough to have the brightest engineers in the industry scratching their heads.
The need to bring in high-k dielectrics at the critical gate oxide layer for the 45-nanometer manufacturing node, and to simultaneously devise ever-lower-k dielectrics to insulate the copper interconnects, will determine whether the chip industry can continue scaling, meeting the power and performance goals outlined by the International Technology Roadmap for Semiconductors (ITRS).
The road map calls for insertion of high-k dielectrics at the 65-nm node in 2006, initially for low-power applications such as cell phones. Toshiba Corp. and NEC Corp. separately have said they intend to do just that, bringing in a hafnium silicate high-k material-a mixture of hafnium, silicon, oxygen and nitrogen-at the latter half of the 65-nm node. Managers say Texas Instruments Inc. is debating whether to introduce its hafnium silicate composition in that time frame too or, as now appears more likely, to wait until the 45-nm node, which for early adopters starts in 2007.
At the back end of the line, low-k dielectrics and copper must be scaled in order to meet interconnect performance goals. Starting in 2007, the road map calls for an effective low-k dielectric-including the barrier, etch stop and nucleation layers-to reach a k-effective factor of 2.7 to 3.0, down from the 3.1 to 3.6 range now. The ITRS goal is a range of 2.3 to 2.6 for next-generation interconnects, coming in at the end of the decade at 45 nm.
Companies at the top of the semiconductor food chain will try to beat those targets by a year or two. But some-although certainly not all-believe the materials now used to insulate copper wiring are so fragile that rapid progress will be more difficult than expected.
The front-end processing section of the 2003 edition of the ITRS sums up the problem: The traditional transistor and capacitor formation materials-silicon, silicon dioxide and polysilicon-have been pushed to fundamental material limits. "We have entered the era of material-limited device scaling," the road map's authors declared.
The transition is complicated by the fact that for high-performance chips, dual-doped polysilicon gates, currently the mainstay of CMOS technology, will need to be replaced by dual metal gates in order to deal with polysilicon depletion and mobility degradation.
Low-power applications are likely to stick with polysilicon gates, largely for cost reasons, said Gregg Higashi, chief technology officer for front-end processes at Applied Materials Corp. (Santa Clara, Calif.). The low-power community will continue to use metal oxide chemical-vapor deposition tooling for hafnium silicate deposition, again to save cost and minimize complexity, he said.
High-performance chip vendors will use different metals for the NMOS and PMOS gate electrodes, processing each transistor somewhat differently, in an effort to limit mobility degradation problems with the hafnium-based oxides. To keep the oxide and interfacial layers extremely thin, they are likely to use atomic-layer deposition tools.
The good news is that the industry has coalesced around a material-hafnium-and integration work is well under way. Following that will come reliability studies, Higashi said.
In a keynote speech last month at the International Reliability Physics Symposium in Phoenix, Texas Instruments CTO Hans Stork termed gate oxide scaling "the most difficult challenge facing the industry." Chip manufacturers, he said, "have to pay attention to TDDB [time-dependent dielectric breakdown]. How these materials degrade, whether they go through a graceful degradation or suddenly go kaput, is an important issue facing the reliability community." But Stork said more progress is needed in the areas of electron mobility degradation and threshold voltage shifts from the high-k materials.
Success depends on achieving an optimum equivalent oxide thickness (EOT), with "equivalent" referring to what the thickness would be if pure silicon dioxide were used, rather than a high-k material. At the interface between the gate electrode and the oxide, and at the bottom interface between the oxide and the channel, "interface engineering" is particularly critical to meeting leakage and performance specs. A thick interface worsens the EOT. A too-thin interface can result in unacceptable mobility degradation as electrons move across the channel.
Chuck Ramiller, director of the front-end processes (FEP) division at International Sematech (Austin, Texas), said full characterization of the high-k materials is a work in progress, with "the measurement technology still evolving" to determine voltage instability and mobility characteristics. One encouraging development is that the high-k materials under evaluation "meet the raw EOT numbers that we need," Ramiller said: approximately 6 to 8 angstroms for high-performance applications and roughly double that for low-power chips. The good news is that leakage currents are perhaps 1,000 times better than for SiO2-based oxides.
For nitrided silicon dioxide, best known as oxynitride, "the consensus is that 12 angstrom is pretty much it, as far as gate leakage characteristics are concerned," said Ramiller, an IBM assignee to Sematech. By going to a high-k material such as hafnium silicate, a thicker physical layer, of approximately 30 to 40 angstrom , is achieved.
Researchers based at the 10 universities that participate in the FEP Transition Center, coordinated by North Carolina State University, are studying oxides based on aluminum, zirconium, lanthanum and other metals. Mobility degradation, however, appears more severe with compounds based on those metals.
Buoyed by $40 million in funding from the state of Texas for its Advanced Materials Research Center, Sematech recently stepped up its research effort into metal gates.
Some companies are considering using metal gates with today's oxynitrides, Ramiller said. By removing polysilicon depletion from the equation, the EOT of the familiar oxynitride improves by several angstroms. And rather than use separate metals for the PMOS and NMOS, with the additional process complexities, some companies are investigating fully silicided metal gates, in which dopants are used to engineer the work function of the polysilicon before it is fully silicided, replacing the polysilicon with the doped silicide metal.
"Metal gates reduce polysilicon depletion, but there are integration questions," said Larry Larson, associate director of the FEP division at Sematech. "Bringing in metal gates has a significant effect on the process flow."
Larson cautioned that metal gate research is "really wide open" for the PMOS transistor, with companies still searching for the best metal candidates. At the NMOS side, tantalum and titanium nitride metals are the leading candidates.
Asked if high-k dielectrics were on track for introduction, Larson said, "We now have candidate solutions out there that we can do electrical characterizations on. That itself is quite an accomplishment. Two years ago, we were not in a position to do that." He cautioned, however, that "it's like peeling an onion; sometimes things are not so pleasant the closer you get to the center."
Larson said low-power transistors can get by with a higher EOT. That means they can use a thicker interfacial oxide, which solves many of the mobility degradation problems. "It is looking extremely hopeful for the low-power route, because low-power transistors have a much less aggressive EOT goal than the high-performance devices," he said. "That allows you to get around the interface issues that affect mobility. The thicker EOT allows you some latitude there."
The EOT at the gate oxide directly affects drive current: The shorter the channel, the higher the drive current. But the gate oxide thickness must scale proportionately with the length of the channel to keep the transistor performance in balance, Larson noted.
At high frequencies, charge trapping in high-k oxides appears to have an impact on electron mobility, an issue that was the subject of several presentations at the International Reliability Physics Symposium. At high temperatures, high-k dielectrics appear to suffer from trap-assisted mechanisms in which carriers hop from one trap (or oxide defect) to another, said Guido Groeseneken, a reliability engineer at the Interuniversity Microelectronics Consortium (IMEC; Leuven, Belgium). Also at high temperatures, the carriers hop from trap to trap much faster, increasing two orders of magnitude at 100 degrees C and higher.
As a result, according to an IMEC study, stress-induced leakage current appears to be an issue for hafnium oxide dielectrics at the relatively high temperatures experienced within server microprocessors and other high-performance chips. The issue appears to be less serious for the hafnium silicates. Nonetheless, Groeseneken said, it is generally believed that the hafnium silicates do not have high-enough k-values to satisfy the requirements of high-performance transistors, which need to drive the EOT-including the interfacial oxide layer of 2 to 5 angstrom (0.2 to 0.5 nm)-to about 8 angstrom (0.8 nm).
At Singapore's Silicon Nano Device Laboratory, optimistic reports are surfacing about progress with high-k dielectrics. "For the PMOS devices, Toshiba is reporting that threshold voltage stability issues are coming under control," said researcher Yoo Won Jong.