The translation of logic levels is made necessary by the growth of digital ICs that feature incompatible voltage rails, lower Vdd rails, or dual rails for VCORE and VI/O, and the use of mixed-signal ICs whose lower supply voltages have not kept pace with those of their digital counterparts.
Translation methods vary according to the range of voltages encountered, the number of lines to be translated (4-line SPI versus a 32-bit data bus, for instance), and the speed of the digital signals. Many logic ICs have the ability to translate from high-to-low levels (such as 5V to 3.3V logic), but fewer can translate from low to high (3.3V to 5V). Level translation can be accomplished with discrete single transistors or even with a resistor-diode combination, but the parasitic capacitance inherent in those methods can reduce the data-transfer rate.
Although byte-wide and word-wide level translators are available, they are not optimal for the <20mbps serial="" buses="" covered="" in="" this="" article="" (spi,="">20mbps>2C, USB, and the like). Such devices, which require large packages with high pin counts and an I/O-direction pin, are not meant for small serial and peripheral interfaces. Higher-speed buses such as Ethernet, LVDS, and SCSI have their own physical layer, and are not covered here.
The SPI (Serial Peripheral Interface) consists of the unidirectional control lines Data In, Data Out, Clock, and Chip Select. Data In and Data Out are also known as MISO (Master In, Slave Out) and MOSI (Master Out, Slave In). SPI can be clocked in excess of 20Mbps, and is driven by CMOS push-pull logic (Figure SB2 in the Sidebar). Being unidirectional makes level translation simpler. Because you don't have to translate in both directions on the same signal line, you can employ simpler techniques involving resistors and diodes (Figure 1) or discrete/digital transistors (Figure 2).
Figure 1. Resistor-diode topology.
Figure 2. Digital transistor.
Level translation for bi-directional buses like I2C/SMBus and Dallas Semiconductor's 1-wire is more difficult, because one must translate in both directions on the same data line. Resistor-diode and single-stage-transistor translators don't work because they are inherently unidirectional. The I2C, SMBus, and Dallas Semiconductor's 1-Wire are all bi-directional, open-drain I/O topologies. I2C has three speed ranges: standard mode at ≤100kbps, fast mode at ≤400kbps and high-speed mode at ≤3.4Mbps.
Unidirectional high- to low-level translation
To translate from higher to lower logic levels, IC manufacturers produce a range of devices that claim to tolerate overvoltage at their inputs. A logic device is said to be input-overvoltage protected if it can withstand (without damage) an input voltage higher than its supply voltage. Such input-protected devices simplify the task of translating from higher- to lower-Vcc logic while increasing the signal-to-noise margin.
As an example, overvoltage-tolerant inputs allow a logic device to cope with logic levels of 1.8V and higher while powered from a 1.8V supply. Devices in the LVC logic family, which are mostly input-overvoltage protected, work well in applications requiring high-to-low translations. The opposite situation of low-to-high translation is not so easy (Figure SB3 in Sidebar). It may not be feasible to generate higher-voltage logic-level thresholds (VIH) from lower-voltage logic.
When designing a circuit for which connectors, high fan-out, or stray load capacitance produces a high-capacitance load, you should keep in mind that for all logic families, reducing the supply voltage also decreases the drive capability. An exception occurs between 3.3V CMOS or TTL (LV, LVT, ALVT, LVC, and ALVC), and 5V standard TTL (H, L, S, HS, LS, ALS): for those families, the 3.3V and 5V logic activation points (VOL, VIL, VIH, and VOH) match each other.
Mixed high-low and low-high translation
Applications such as the SPI bus require a mixture of high-low and low-high translation. Consider, for example, a processor at 1.8V and a peripheral at 3.3V. Though it is possible to use a mixture of the techniques described above, a single chip such as the MAX1840/1841 or MAX3390 can implement the necessary translation by itself (Figure 3).
Figure 3. IC level translator with SPI/QSPI/Microwire interface.
Other systems, such as I2C and the Dallas 1-wire bus, require logic translation in both directions. Simple topologies based on a single transistor with open collector or drain will not work in a bi-directional bus because they are inherently unidirectional.
Bidirectional transceiver methods
For the larger byte- and word-wide buses, where WR and RD signals already exist, one method for transferring data across the voltage levels is a bus switch such as the 74CBTB3384. Such devices tend to be optimized for operation between 3.3V and 5V. For smaller 1- and 2-wire buses, this solution raises two issues: It requires a separate enable pin to control the direction of data flow, which ties up valuable port pins, and it requires large ICs that take up valuable board space.
All techniques have their pros and cons, but designers need a universal device that works across all translation levels, enables mixed low-to-high and high-to-low logic transitions, and includes uni-directional and/or bi-directional translation. A next-generation bi-directional level shifter (MAX3370 of the MAX3370-3393 family of ICs) fulfills those needs. At the same time, it overcomes some of the problems associated with alternative approaches.
The MAX3370, which implements a transmission-gate method of level translation (Figure 4), relies on external output drivers to sink currentÔ¾whether they operate in a low-voltage or higher-voltage logic domain. That capability enables the device to work with either open-drain or push-pull output stages. Moreover, the relatively low on-resistance of a transmission gate (less than 135Ω) limits the speed of operation much less than does the series resistor of Figure 1.
Figure 4. MAX3370 level translator.
Figure 4 offers two other advantages: For open-drain topologies, the MAX3370 includes 10kΩ pull-up resistors paralleled by a "speed-up" switch, which minimizes the need for external pull-up resistors while reducing the RC time-constant ramp associated with traditional open-drain topologies. The tiny SC-70 package also conserves valuable board space.
Solving the speed problem
RC time constants limit the effective data rate for most other open-drain approaches (Figures 5-6). Devices of the MAX3370 family include a patented speed-up scheme that actively pulls up rising edges, thereby minimizing the effect of capacitive loads. That effect can be seen in Figures 7-9. When the input goes above a predefined threshold the device actively pulls up the rising edge, thereby minimizing any skew caused by external parasitic components. That effect can allow data rates as high as 20Mbps for signals produced by a push-pull driver. The speed of signals from open-drain drivers tend to be slower. As for other open-drain topologies, however, you can improve their speed by adding external pull-up resistors.
Figure 5. Scope plot of single FET open-drain output at 20kHz.
Figure 6. Scope plot of a dual-transistor transceiver translating 1.8V to 5V at 400kHz (a) and 100kHz (b).
Figure 7. Scope plot of MAX3370 output, translating 1.8V to 5V at 400kHz.
Figure 8. Scope plot of MAX3370 output at 400kHz, with 4.7kΩ pullup resistors.
Figure 9. Scope plot of output from high-speed test circuit.
Solving the universal voltage problem
Ideally, an application requires a single component that can translate between any two logic levels and at any speed. ICs of the MAX3370 family have been designed for logic levels as low as 1.2V and as high as 5.5V. That capability allows a single component to provide the level translation required in most cases, without the need to pick a logic device for each level-translator requirement.
Earlier, the need for low-to-high and high-to-low translations in the same circuit could be met only with separate chips, but the bi-directional and topology-independent features (push-pull or open-drain) of a single chip from the MAX3370 family solves both problems. The MAX3370 is a single-line universal logic level translator. For translating a larger number of I/O lines, see the devices listed in Table 1.
Table 1Ô¾Multiline logic-level translators.
As the number of I/O voltages per system increases, the need for level-translation techniques becomes more acute. Compounding the problem are load capacitance, the magnitude of Vcc differences, and speed. For high-to-low translation the problem is less acute if the difference in translation voltages is minimal, and if off-the-shelf devices (such as logic ICs tolerant of input overvoltage) are available.
It becomes difficult, though, to find ICs and discrete-component circuits capable of handling ICs with wide differences in Vcc, and of translating from low to high logic levels. Bi-directional and open-drain topologies do not lend themselves well to high-speed data rates. Maxim level translators ease the problem of level translation for a wide range of bi- or uni-directional, push-pull, and open-drain topologies. The ICs are available in ultra-small packages and require no external components for standard operation.
SPI is a registered trademark of Motorola, Inc.
I2C is a registered trademark of Philips, Inc.