# Summing the errors: Voltage offsets revisited

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Of all the pieces I have written over the life of this column the one that has drawn the biggest response from you, the readers, was the one on amplifier voltage offset ("Will the real offset voltage please stand up, August 24, 2004). Many of you thought I left the tale half told because I did not mention the effect bias current through the gain resistors, had on the total offset. Another segment of the readers had comments on the root-sum-square collection of the error terms that was presented at the end of the column.

To finish accounting for the DC error terms in an amplifier application the designer should consider the contribution due to the input bias current. The actual calculation of the bias current effect depends on whether the inverting and non-inverting input bias currents are independent or share a commonality. If the input devices are FETs, or if a bias current cancellation sub-circuit has been implemented then the offset contribution can be calculated with this model.

The bias current at the positive input will cause an offset voltage as it flows through the parallel combination of R_{3} and R_{4}. This will appear as a signal at the non-inverting input and be magnified by the non-inverting gain of the amplifier. As the amplifier will keep the inverting pin at the same potential as the non-inverting pin all of the inverting input bias current will flow through R_{2}. As these currents may be of the same or opposite polarity the worst-case result will be to simply sum them. The output voltage due to bias currents is:

It is common for this value to be so small that it can be ignored.

However, in the case of those op amps with a bipolar transistor input stage and no bias current cancellation scheme the results can be significantly different. This change is caused by the fact that the bias currents in each of the inputs flow in the same direction. Therefore the sign changes in the equation from plus to minus. With this change, if the resistors are selected such that the parallel combination of R1 and R2 is equal to the parallel combination of R3 and R4, the output voltage is:

In these amplifiers the value of i_{os} can be as low as 1/10th the value of i_{b}.

My second point in the previous column dealt with the method of collecting the various error terms. Several readers took exception to the light gloss with which I covered the root-sum-square approach vs. the direct summation where I contrasted applications between a toy and an airplane. Thanks to my readers I now have a solid foundation in the central limit theorem and its application to accounting for the error terms. However, I am more of a practical engineer than a theoretician and so I suggest the real answer is in the economics. What is the cost of having a part that is slightly over tolerance? Will the circuit be tested at a subassembly stage and is a repair possible before the subassembly advances? The practical engineering solution would be to compare the cost of the occasional repair or the cost of being slightly out of spec, against the cost of higher precision parts to be sure the worst-case error stack was within the error budget.

Thanks for readingComments Please.

klein_bill@ti.com

And be sure to copy, you-know, sohr@cmp.com