In recent years, as capacity requirements for digital transmission systems have increased, there has been a trend to replace parallel bus architectures with very high-speed serial lines. Although the transmission distances may be less than a meter, the design of such a link has many similarities to communication systems that span several meters or even tens of kilometers.
The basic blocks for these systems include a transmitter, a channel, and a receiver. When a serial link is designed, whether for a communications system or a serial bus, the three elements of the system are usually specified individually so that when the entire system is put together, an overall performance level can be achieved. In a digital communications system the key specification is bit-error- ratio (BER). Transmitters are generally specified to have a certain waveform performance quantified by parameters such as eye-diagram opening, edge speeds, and power or voltage levels.
Figure 1: Phase and frequency shifts in a transmitted signal may make a serial data pattern difficult to read..
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Bit Error Rate sets the bar
The receiver is specified a bit differently. In many systems, receiver performance is defined to guarantee that it will be able to always achieve the desired system BER level as long as the incoming signal meets a minimum performance level. As might be expected, this minimum acceptable performance level is often described in terms similar to the transmitter specifications. This can be better understood by examining how a high-speed digital receiver operates. In its most basic form, the receiver is a decision circuit. Its primary function is to decide if the incoming bits are logic 1's or logic 0's. The decision process is made easier and with less chance of error if the voltage or power separation between the incoming logic levels is as large as possible. This partially drives the specification of the transmitter. But it also drives the specification of the receiver. Given that there must be a reasonable limit to the signal levels the transmitter can achieve, and that the signal will be degraded going through the channel, there will be tradeoffs between how big the transmitted signal must be and the smallest signal that a receiver must be able to accurately interpret.
A critical aspect of the receiver circuit decision process is ensuring that the decision process occurs at an optimal time. This is most critical when a logic 1 is preceded or followed by a logic 0, or when a logic 0 is preceded or followed by a logic 1. In these cases, it is usually ideal for the decision to take place at the center of the bit period. For example, if the incoming bit stream is a 0, a 1, and then a 0, it will be critical that the decision does not take place close to where the signal is switching between amplitude levels such as the 0 to 1 transition or signal "edge." If the decision takes place near the edge, the likelihood of a bit error increases dramatically.
Some form of clock signal must be provided to the decision circuit to time the decision process. If the incoming data stream is at 1 Gbits/s, then a 1 GHz clock is needed. But not just any 1 GHz signal will suffice. This signal must be highly synchronous with the incoming data stream. Just a small offset in frequency between the data rate and the receiver clock will cause the decision point to slip from its ideal time location and degrade the BER. Thus, the receiver clock signal is extracted directly from the incoming data stream.
The key analog element
A clock extraction circuit is often based upon a phase-locked-loop (PLL) architecture. A voltage-controlled oscillator (VCO) initially runs at a frequency close to the expected data rate. Part of the VCO signal is routed to a phase detector, which will compare the phase of the VCO signal with a portion of the incoming data stream. If the VCO is not at the same rate as the data signal, the phase detector will produce an error signal which is proportional to the frequency difference.
Figure 2: A VCO provides a reference frequency for PLL-based clock
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This error signal is used as a controlling signal at the VCO to adjust its frequency and force the VCO to match or "lock" to the incoming data signal. The receiver circuit now has the criti cal capability of timing its decision circuit at exactly the rate of the data and in the center of the bit period for optimal BER performance.
Removing the jitter
The incoming data stream is likely to have some small fluctuations above and below its ideal rate. These fluctuations are commonly referred to as jitter. The receiver PLL must be able to respond to changes in the data rate so that the decision circuit continuously operates in the center of the bit. The ability of the PLL to tolerate jitter is determined by the bandwidth and gain of the VCO/phase detector feedback loop. The PLL then must have adequate bandwidth or loop response speed to keep up with the anticipated rates of jitter. Thus a third aspect of the PLL design is the control loop.
Figure 3: Triggering the receive circuit with the extracted clock removes common jitter.
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The VCO can be thought of as a flywheel that is kept spinning at the desired rate by incoming bit transitions. That is, whenever there is a change from a 1 to a 0 or a 0 to a 1, the VCO has something to synchronize to. It is important for the VCO to stay on frequency even when there are no transitions such as when there is a long run of 0's or a long run of 1's. This is achieved by placing an effective low-pass filter between the output of the phase detector and the control input of the VCO. This provides stabilization to the VCO control signal and subsequently the VCO frequency. It would seem that the higher the stability, the better. But consider also that the filter controls how fast the jitter on the incoming data can be and still allow the VCO track and follow. When the data signal has jitter, the error signal output of the phase detector will be an analog representation of the jitter.
The phase detector is effectively a jitter demodulator. Since the error signal controls the VCO, the jitter from the data is transferred to the VCO. Again, this is the desired result to allow the decision circuit to stay synchronized with the data. If the rate of jitter becomes fast enough (relative to the bandwidth of the control loop), the rapidly varying error signal from the PLL phase detector will be suppressed by the loop filter. High frequency jitter does not reach the VCO. Thus the PLL, and subsequently the receiver using this PLL, can only tolerate data with jitter frequencies that are within the bandwidth of the loop filter. There is an optimal range for the loop bandwidth of the clock recovery circuit. It must be wide enough to track out the expected jitter, but low enough to not respond to low transition density data sequences. This then requires another look at the specifications of the transmitter.
If there is excessive high frequency jitter, the receiver will not be able to respond quickly and adjust the sampling time to the center of the bit period. A common approach is to specify that transmitter jitter that is at high frequencies cannot exceed a certain magnitude. This approach takes into account that the receiver PLL should easily tolerate low frequency jitter. By not penalizing a transmitter for having low frequency jitter, the cost of the transmitter should be reduced.
Measuring transmitter jitter can be achieved many ways, the most common method being with an oscilloscope. The eye-diagram is an overlay of all the bits of a datastream, overlapped on one another on a common one bit period time axis. If the signal is jitter free, all the 1 to 0 transitions will occur at the same time, and all the 0 to 1 transitions will occur at the same time. The eye diagram cros sing point (where the 1 to 0 transitions intersect with the 0 to 1 transitions) will have a very narrow width. If there is signal jitter, the transitions will occur at different times due to the varying data rate. In the eye-diagram this is observed as a thick crossing point. Note that in this analysis, there is no way to know how fast the jitter is, but only how large the jitter is.
Trigger on the recovered clock
One technique to filter out the low frequency jitter and observe only the high frequency jitter is to use an advanced technique for triggering the oscilloscope. A trigger signal is used by the oscilloscope to determine when the data is actually measured. The X axis of the oscilloscope is time "relative to the triggering event," the Y axis is signal amplitude. Similar to the clock used in the communications receiver to determine when to fire the decision circuit, a trigger signal is often a clock that is synchronous to the data being measured. A trigger event is usually defined to be when the trigger signal crosses a defined amplitude threshold.
If the oscilloscope is triggered with a spectrally pure, jitter free clock signal running at the same nominal rate as the data signal, any jitter present on the data is observed as a broad crossing point in the eye diagram. The crossing point width is a direct indication of the magnitude of the jitter, relative to the jitter free trigger signal. But what would be observed if the signal triggering the oscilloscope was derived from the data stream being measured? To understand this, recall the discussion on receiver PLL's above. When a clock is extracted from the data, it will include the same jitter that was present on the data, as long as the rate of the jitter was within the loop bandwidth of the PLL.
When jitter on the trigger is the same as the jitter on the signal being measured, that jitter is effectively common moded out of the displayed waveform. Remember that the jitter that is most important to be observed is the jitter that the receiver decision circuit in the communications system cannot tolerate.
Very wide bandwidth oscilloscopes have the built-in ability to extract clocks from the signals being observed. Advanced clock recovery schemes allow the loop bandwidth to be adjusted to control the spectrum of the jitter observed on the waveform. For example, if the loop bandwidth is set to 100 kHz, jitter that is below 100 kHz will be common to both the data and the trigger signal. This jitter will not be observed. Jitter that is above 100 kHz is not passed to the recovered clock trigger. It will be present only on the data signal and will be displayed. This indicates an unusual effect of the loop bandwidth filter in the clock recovery PLL. This is a low pass filter. However, from the perspective of the observed jitter on the oscilloscope, it has a high pass effect. Only jitter that is above the bandwidth of the filter is observed. This then provides a solution to the transmitter test problem discussed above. By using a clock extraction circuit in the oscilloscope with performance similar to the receiver PLL, the jitter observed during testing of the transmitter is the jitter that the system receiver cannot tolerate.
Using a "Golden PLL"
When system compliance test specifications are set for transmitters, a clock extraction circuit with a specific loop bandwidth is often dictated. This is sometimes referred to as a "Golden PLL." Figure 4 (left) shows an eye diagram with obtained with a jitter free clock trigger, while Figure 4 (right) shows the same signal observed with a golden PLL trigger. Note how the eye of Figure 4 (right) has significantly less jitter and a wider opening than the eye of Figure 4 (left). Again, the eye of Figure 4 (left) is a more accurate representation of the signal that a receiver decision circuit would see.
Figure 4: The eye pattern generated by a jitter-free reference clock (left) doesn't tell you what the receiver is getting. Triggering on the extracted clock (right) provides a more accurate picture.
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A subtle but important element of the test system golden PLL is that it needs to have a specific loop BW for a variety of data patterns. Specifically, for consistent test results, the bandwidth should not change even if patterns with low or high transition densities are used. Thus the loop gain (which affects loop bandwidth) needs to monitor the pattern and adjust gain to match the data pattern transition density. Also, while the golden PLL solves the compliance test problem to screen out excessive high-frequency jitter, it can present a problem for someone trying to examine the total jitter of a transmitter. This problem is also solved through adjustable loop gain in the clock extraction circuit (which controls bandwidth). Reducing the loop BW allows more of the jitter spectrum to be observed.