CHARLOTTE, N.C. -- The IC design and test community's quest to achieve fewer than 100 defective parts per million (DPPM) is becoming more difficult as process technologies move below 100 nanometers.
Among the issues raised at the 90-nm process level are whether the 100-defect benchmark is achievable or whether the metric is practical. The cost of reaching the 100-defect level also remains a concern.
Manufacturing and test experts at the International Test Conference here this week (Oct. 24-29) said there are legitimate reasons for getting under the 100-defect limit and that the goal is justified in some applications. "It's the customer that drives the [defective parts per million]" debate, said Brady Benware, senior product engineer at LSI Logic (Fort Collins, Colo.).
"The challenge is not whether 100 DPPM can be achieved, it can. The real challenges are being able to deliver this quality level from the first prototype lot, not impacting the design cycle time and minimizing test cost such that profit margins can still be met," he added.
In sub-100-nm designs, Benware said structural testing of nearly perfect stuck-at fault and transition-delay fault coverage is insufficient. Many defects cannot be adequately described by either fault model. "The bottom line is that to ensure a repeatable and cost effective realization of 100 DPPM with structural-based test, a mixture of deterministic and statistical or pseudorandom patterns will be required," said Benware.
Traditional methods using simple fault models and pass/fail testing will have to be abandoned in favor of probabilistic and statistical approaches, said Texas Instruments Inc. Fellow Kenneth Butler. "We have long relied on the fortuitous nature of detection. Tests will have to be altered so that the likelihood of fortuitous detection is increased," Butler said.
That increase is accomplished by diversifying test excitation conditions while still being able to measure the test results, Butler added. He said more test types must be applied, such as various types of at-speed tests and very low and high voltage tests.
The goal of fewer than 100 defects is achievable, but it will drive schedules, costs and resources -- making it unacceptable for some products, said Phil Nigh, a senior member of IBM Corp.'s technical staff (Essex Junction, Vt).
Nigh distinguisheed ICs produced for internal IBM consumption with those provided to OEM customers. "It's a learning experience we have to go through with our external customers to convince them that maybe 100 DPPM is a not necessarily a goal for their product."
Nigh questioned whether the 100-defect level is worth the effort. "It's really, really hard to achieve," he said. "You can take all the testing methods described in the [conference] proceedings and apply them, and you might have a shot at 100 DPPM."