While there is much debate over the value, definition, viability and technology of design-for-manufacturing (DFM), all of it is chip based. Certainly, chip DFM is a crucial requirement as we start thinking about 45- and 32-nanometer designs. However, by focusing on chip DFM, we are ignoring an even more critical technology imperative: DFM for printed circuit boards (PCBs).
We all know that even if the silicon is 100 percent perfect, the target system may still not function properly, if any component (such as the package, connector, or PCB) in the chip-to-chip communication link is broken. Many package, connector, and PCB vendors might be urged by system designers to tighten their manufacturing tolerance.
But, unless all vendors tighten their specifications in concert, a connector with plus/minus 5 percent tolerance, for example, may not do much good to a system with a PCB at plus/minus 10 percent tolerance. To optimize a system's design, the designers will need to study the cause and effect of each component. So far, we don't have DFM tools to handle design problems such as this.
During the pre-layout design stage, the high-speed system or signal integrity engineer can usually afford to perform only a limited set of Spice simulations. To make sure that the system will work well in the field, the corner cases that cover all manufacturing tolerances need to be simulated.
For example, variations of the metal trace width, dielectric stack height, dielectric constant, and loss tangent in a PCB can all affect impedance and attenuation. However, only engineers at larger companies may have the resources to customize their own scripts to launch thousands of simulation jobs and post-process the results. Even then, there is no well-defined standard as to what variables to sweep.
Perhaps the most conspicuously absent are the corner models of package and connector. For high-speed design, these models can be defined accurately only through frequency-dependent S-parameters. However, very few package and connector vendors provide good nominal S-parameter models, let alone the corner models over a wide frequency range.
During the post-layout verification stage, accurate extraction and simulation of complex PCBs need to be performed, to account for the detailed corners and bends. Again, few tools are available to perform such accurate extraction and simulation, let alone accommodate the variation of metal trace width and dielectric stack height, etc.
It's clear that a common PCB design and verification methodology is needed. So what do we need?
Let's focus on two areas, just to get started on DFM for pc boards. For pre-layout designs, it is desirable to have, for example, a GUI-driven schematics entry editor that allows the designers to easily enter the variation of each component, launch the simulation, process the results, and report the cause and effect of each variable. Based on the sensitivity data, the engineers can then tune their designs and get the "biggest bang for the buck."
For post-layout verification, a DFM tool needs to be able to adjust the layout automatically to cover the corner cases, apply a fast full-wave extractor to extract the parasitics, and simulate the parasitics with I/O transistor corner models in circuit simulation.
Only after engineers include manufacturing tolerance in both design and verification, can they say they have done their design for manufacturing. And only when tool vendors realize that the chip is just a part of a sub-system—such as a PCB—will this current brouhaha about DFM finally and realistically become relevant to customers who develop end-products.
Until then, DFM just for chips is like checking to see if a tire is flat when the whole suspension system of a car needs to be checked out.
Ching-Chao Huang is president of AtaiTec Co., a signal integrity software and consulting company based in San Jose, Calif.