On June 28, LSI Logic announced its Core in I/O methodology, which the company states provides optimal use of core and I/O area for logic design, and an improved design experience. The methodology enables flexible and optimized I/O placement in Platform ASIC and cell-based ASIC/SoC design by allowing core logic to be placed in the I/O regions.
On the heels of LSI's Pad on I/O and flxI/O which allowed for the placement of bond pads on top of active circuits in wirebond, and area arrayed signals in flip chip designs respectively, the Core in I/O methodology provides smart management of I/O assignment, unlocking the I/O ring to extend density advantages previously offered, optimizing silicon area. Benefits claimed include providing maximum silicon area to place gates, memory, and LSI Logic CoreWare IP on-chip, and unprecedented ASIC SoC design solution density.
According to Stan Mihelcic, director of Advanced Packaging and I/O Technology, Technology Marketing, "The introduction of the Core in I/O methodology is an industry first for nanometer SoC designs. LSI Logic's co-design technology provides IC designers with the industry's most effective, densest design solutions that ensure optimal use of the silicon design area that's available today." Mihelcic also stated that the methodology is yet another that provides SoC designers the ability to take full advantage of the integration capabilities of Gflx and G90 Platform ASIC and cell-based offerings.
Core in I/O methodology is based on LSI's FlexStream and RapidWorx design systems. The scheme includes analysis of physical, electrical, and interconnect constraints of I/O and package connection, providing floor-planning flexibility to reduce routing and placement congestion. Additional benefits cited are a better design experience and more optimal and efficient design solutions.
The methodology is independent of I/O aspect ratios, enabling flexibility in the use of multiple I/O architectures and libraries. The technology is optimized for low-cost wirebond packaging solutions used in consumer, storage, and office automation markets where cost effectiveness is critical. Used in conjunction with Pad on I/O technology, significant reduction in die size is achieved, compared with conventional chip design solutions. The methodology is currently available for Gflx and G90 cell-based ASIC and Platform ASIC design platforms.