A networking reference design for Altera's Nios II delivers 60 Mbits of throughput via TCP/IP over a 100-Mbit link for embedded applications requiring high-throughput network connectivity.
"The versatility and performance of our NicheStack IPv4 protocol suite addresses the challenges faced by embedded systems development teams," said Larry Larder, president of InterNiche. "By enabling low-cost TCP/IP connectivity on FPGA designs with exceptional performance, we help to open up a new world of flexibility for the system designer."
Daniel Koehler, MorethanIP CTO explained that its Ethernet MAC with integrated hardware network protocol acceleration (MAC-NET core) increases performance and that together with the InterNiche embedded TCP/IP provides Nios II designers with a highly optimized, scalable, full-featured solution.
Using the MAC-NET core and IPv4 software stack, embedded designers can use Altera's SOPC Builder and Nios II integrated development environment to customize their reference design. The reference design features a Cyclone EP1C12 FPGA, a ready-to-use demo, MAC-NET, and NicheStack IPv4.
The MAC-NET core supports 10/100/1000 Mbit Ethernet connections and incorporates a layer _ high-performance checksum block to accelerate network operations supporting InterNiche's NicheStack IPv4 and IPv6 with TCP and user datagram protocols. NicheStack IPv4 provides a configurable TCP/IP protocol suite equipped with a complete range of management and security protocols including simple network management protocol, SSL, IPsec, and embedded HTTP server.
According to Chris Balough, Altera director of software and Nios marketing, "Embedded designers will be able to leverage the flexibility and performance of the MAC-NET core and NicheStack IPv4 protocol suite for their FPGA-driven network connected products."
The reference design, the Nios II embedded processor and the complete evaluation toolset can be downloaded from Altera's Web site.