Carbon Design Systems specializes in high-performance virtual system prototyping (VSP) solutions that enable system prototypes to be rapidly assembled and functionally validated on the desktop months before silicon becomes available. Carbon's software approach allows multiple levels of abstraction to be validated together, including C, SystemC, RTL, IP cores, transaction-level, and instruction-level models. Such VSPs have the ability to execute billions of cycles and boot embedded operating systems, all with desktop software.
Although Carbon's VSP technology is predominantly associated with traditional standard cell ASICs and SoCs, it is also applicable to Structured ASIC implementations.
Now, Pacific Design's configurable VUPU processor and accompanying instruction set simulator is available on Carbon's VSP validation platform. Pacific's VUPU is the combination of a general purpose RISC processing unit and one or more variable-cycle data path execution units or VUs. These VUs are high performance data path co-processors that are configured after profiling the user's software with Pacific's MAX profiler. These VUs can also be provided by the user as predefined RTL macros. In a virtual system prototype, the processing unit is modeled as an ISS. The VU hardware functions and any other RTL hardware blocks are automatically compiled by VSP into virtual silicon models. This high-speed ASIC / SoC / Structured ASIC validation environment enables embedded software to be validated on a silicon accurate model of the system. Mixing levels of abstraction provides both the performance and accuracy necessary to validate the most complex designs. On a recent customer design, the software validation runtime was dramatically reduced from nine hours on a popular EDA simulator to 40 minutes on a VSP.
More information is available at www.CarbonDesignSystems.com.