Lattice Semiconductor Corporation has announced the availability of a free display interface reference design that illustrates how to use the pre-engineered I/O components within its low cost LatticeECP2 and new LatticeECP2M FPGA families (collectively referred to as "LatticeECP2/M" devices) to implement the "7:1" source synchronous LVDS (Low Voltage Differential Signaling) interfaces commonly found in display applications. Lattice also announced its plans for a series of daughter boards that can be used with the existing LatticeECP2 Advanced Evaluation board to quickly test this reference design for display applications. By integrating the 7:1 LVDS interfaces within its FPGAs, Lattice enables designers to reduce component count and system cost.
"Our LatticeECP2/M devices offer a compelling value proposition to customers seeking selected high performance features, such as SERDES, on a low cost FPGA fabric," said Stan Kopec, corporate vice president of marketing. "This reference design illustrates how the high performance I/O capabilities of our LatticeECP2/M FPGAs can be used in display applications for the consumer, automotive and industrial instrumentation markets."
7:1 LVDS interfaces
Display applications require the transfer of large amounts of data across multiple boards within a system. Often this transfer is implemented with high-speed LVDS interfaces that typically consist of three or four data lines and a clock. Seven data bits are transmitted for every clock period, and commercially available parts support clock rates of 85MHz and beyond, which translates into data rates of 595Mbps and higher.
There are three key challenges associated with implementing high-speed 7:1 LVDS interfaces within FPGAs. First, a high-speed LVDS buffer is required. Second, high-speed data streams need to be serialized and de-serialized. Third, the skew between data and clock bits must be managed in order to avoid eroding the timing margin.
Pre-engineered I/O components simplify implementation
The display interface reference design takes advantage of the LatticeECP2/M devices' pre-engineered components that simplify the implementation of 7:1 LVDS interfaces. The LatticeECP2/M FPGAs contain integrated LVDS receivers and drivers capable of 840 Mbps performance. Built-in gearbox logic allows a 4X reduction in data rate before the data enters the Look-up Tables (LUTs) at the core of the FPGA. Built-in edge clocks minimize the skew between data and clocks. These pre-engineered components allow 7:1 LVDS interfaces to be easily constructed, without the need for manual placement of LUT logic within the devices. The components also provide more timing margin, which permits a more robust and manufacturable design.
To facilitate testing and evaluation of the LatticeECP2/M devices in display applications, Lattice will make a set of daughter cards available for use with its LatticeECP2 evaluation board. These daughter cards will allow image data from a source device, such as a DVD player or PC, to be passed through other vendors' devices and ultimately be converted into 7:1 LVDS format before being passed though a cable to the LatticeECP2 board. The LatticeECP2 device receiving the data then performs simple image manipulations and passes the data off the board, again using a 7:1 LVDS format. A final board converts the 7:1 LVDS data into DVI format, which is then passed to a display.
Pricing and availability
The high-speed LVDS display interface reference design is available now for free download from the Lattice website at www.latticesemi.com. The display interface daughter cards designed for use with the LatticeECP2 evaluation board will be available for purchase in Q4 2006.
About the LatticeECP2 and LatticeECP2M FPGA families
The LatticeECP2 and LatticeECP2M devices are unique low cost FPGAs that address the need for enhanced DSP, Source Synchronous I/O and improved configuration support within a low cost architecture. The LatticeECP2M device adds SERDES and additional memory capacity.
The LatticeECP2 architecture consists of an array of up to 68K LUTs surrounded by flexible I/O buffers that incorporate pre-engineered I/O support that enables the easy implementation of high performance source synchronous interfaces such as DDR2 at 400Mbps and SPI4.2. Strips of sysDSP blocks pass through the logic array to provide up to 88 18x18 multipliers followed by addition, subtraction and accumulation functions. These blocks run up to 375MHz, providing an aggregate DSP capability of 33 Giga Multiply Accumulates per Second (GMACs). A second strip through the device provides sysCLOCK Delay Locked Loop (DLL) and Phased Locked Loop (PLL) capability, up to 1Mbit of sysMEM embedded memory and enhanced configuration capabilities including support for encrypted bitstreams, dual boot and TransFR I/O.
The LatticeECP2M architecture is similar to the LatticeECP2 but adds up to 16 channels of SERDES optimized for PCIexpress, Gigabit Ethernet, SGMII, CPRI and OBSAI applications. The number of LUTs is increased 30% to 95K while DSP support increases to 168 18x18 multipliers, yielding 63GMACs capability, and memory support increases five times to 5.3Mbits.