Lattice Semiconductor and Silicon Laboratories (a leader in high-performance, analog-intensive, mixed-signal ICs) have announced that they will cooperate in the marketing of ITU G.707 and GR-253-CORE compliant solutions for telecom applications that provide customers with flexibility, high performance and quicker time to market.
LatticeSC and LatticeSCM FPGAs ('LatticeSC/M' FPGAs) provide field programmability and a built-in SONET PCS block to accelerate market entry. Silicon Labs' Si5023 multi-rate clock and data recovery (CDR) device, new Any-Rate Si570 programmable crystal oscillator (XO) and Si5326 Any-Rate precision clock, simplify OC-3/12/48 timing architectures and ensure compliance with SONET/SDH jitter specifications.
LatticeSC/M FPGA devices, with their industry-exclusive SONET flexiPCS block, enable telecom equipment vendors to implement programmable SONET/SDH solutions at a lower cost, lower power and faster time to market. Additional embedded IP is also available on the MACO-enabled LatticeSCM devices to build high performance Packet over SONET (PoS) bridges and gaskets.
Delivering a timing solution that is both jitter compliant and frequency flexible, the Silicon Labs' multi-rate CDR, XOs and clock products can be used in conjunction with the LatticeSC FPGA for a complete SONET solution. The Si5023 multi-rate CDR is able to minimize data jitter associated with the LatticeSC device's SERDES outputs while Silicon Laboratories' crystal oscillator and clock devices provide easily reprogrammable reference clock frequencies to the FPGA.
"Silicon Laboratories is committed to providing customers with easy-to-use timing solutions for the telecommunication market," said David Bresemann, vice president of Silicon Laboratories. "By joining Silicon Labs' innovative timing solutions with a Lattice FPGA, we are ensuring a seamless solution for a challenging design problem for our customers."
"Our LatticeSC/M FPGA devices are the ideal programmable platforms for Packet over SONET, Multi-Service or DWDM FEC line-cards. We are very pleased to announce our cooperation with Silicon Laboratories to provide our mutual customers with programmable TDM solutions that meet the strict performance and jitter criteria for SONET/SDH compliance," said Stan Kopec, Lattice corporate vice president of marketing.
About Silicon Laboratories' Si5023, Si570, and Si5326
The Si5023 Multi-rate CDR attenuates high frequency jitter while performing clock and data recovery from a serial input at OC-48/12/3, STM-16/4/1, Gigabit Ethernet (GbE) and 2.7Gbps forward error correction (FEC) rates. The device does not require an external reference clock for lock acquisition. By leveraging Silicon Labs' proprietary DSPLL technology, the external loop filter components necessary in traditional CDR implementation are eliminated, reducing device sensitivity to board-level noise and improving jitter performance.
The Si570 device is the industry's first user-programmable XO packaged in an industry standard, RoHS-compliant 5×7 mm surface mount package with two extra pins for I2C frequency programmability. The device supports orderable options for temperature stability, APR and output signal format. The Si5326 device is an Any-Rate clock packaged in a 6×6 mm QFN with I2C/SPI interface for input/output frequency and PLL bandwidth programmability. This device is typically used for generating a clean reference clock for transmitting SONET data. Both the Si570 and Si5326 support output frequencies up to 1.4 GHz with ultra-low jitter performance (<0.3 ps-rms typical from 50 kHz to 20 MHz) suitable for 10 Gbps applications.
About the LatticeSC/M FPGA family
The Extreme Performance LatticeSC family is designed to provide the performance and connectivity essential for high-speed applications. Fabricated on Fujitsu's 90 nm CMOS process technology utilizing 300 mm wafers, LatticeSC FPGAs are packed with features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network data path connectivity.
The LatticeSC family offers LUT counts up to 115K LUTs and 32 SERDES channels.
Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.8 Gbps data rates, PURESPEED parallel I/O providing industry-leading 2 Gbps speed, innovative clock management structures, FPGA logic operating at 500 MHz and up to 7.5 megabits of block RAM in a single device.
Lattice's unique Masked Array for Cost Optimization (MACO) embedded structured ASIC blocks also are available on the LatticeSCM devices, delivering pre-engineered, standard-compliant IP functions such as SPI4.2, Ethernet MAC and PCI Express control functions developed by Lattice to shorten end-system time to market.