Verific Design Automation says that Actel has integrated Verific's Verilog and VHDL parsers, analyzers and elaborators to serve as the front end to the Libero Integrated Design Environment (IDE).
Verific's products, used in various Electronic Design Automation (EDA) tools for exploring, navigating, analyzing, documenting and modifying designs, include Verilog, SystemVerilog and VHDL parsers, analyzers and elaborators, as well as a register transfer level (RTL) database. All are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and come with online support and maintenance.
The latest (just-announced) version of Actel's Libero IDE was enhanced to ease the system-level design process for all of Actel's field-programmable gate arrays (FPGAs). Its SmartDesign design entry capability is intended to let designers move to a higher level of abstraction, thereby reducing FPGA design and development time, improving productivity, and speeding time to market. Through a tight integration with Verific's front-end software, designers are able to create and automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components.