Note: Mike Santarini, a former editor at EE Times and EDN (now publisher of Xilinx user magazine Xcell Journal) makes his first guest blog entry for Programmable Logic DesignLine this week. We are looking forward to more contributions from Mike.
This February marks my first full year not reporting on the EDA business. I have to say after reporting on EDA pretty much daily for 13.5 years, it's been tough to sit back as a reader and watch what's been going on (and not report on it). It's truly remarkable how the EDA business has changed over the last few years and especially over the last year. As I look at the stock prices of the EDA companies today, it's really quite remarkable how things have changed in just one year's time.
Synopsys is now the undisputed number one company in EDA with a market cap of $3.4 billion, meanwhile Cadence has a market cap of $1.19 billion after spending more than a decade on top of the EDA world, while EDA's oldest vendor, Mentor Graphics, has a market cap of $445.6 million.
While I'm happy for the folks at Synopsys for moving into the number one spot after many years of fighting for it, I have to say as someone who closely monitored the EDA business for many years, I'm a bit worried about the state of the EDA business as a whole. EDA is after all the $3 billion industry that enables the $300 billion semiconductor industry, which in turn enables the $1 trillion electronics industry. But these days the mighty ant seems to be wobbly in the knees.
Why that is is many faceted and quite complex: the 2000 Hart-Scott-Rodino/SARBOX reforms stunted EDA entrepreneurship and acquisitions, respectively; competing vendors have employed buffet tool and scorched earth tool licensing; and EDA firms are still reluctant to collaborate to make tool flows interoperable. But today perhaps the biggest factor is simply that EDA's historically most lucrative tool space, the leading edge ASIC and ASSP market, is shrinking with no uptick in sight.
While the EDA industry sells tools for all segments of the IC design business (analog, processor, memory and logic ICs), it has traditionally drawn the lion's share of its revenue from selling tools to companies intending to create logic devicesASICs and ASSPswith the latest silicon processes. However, during the last economic downturn, the dot com bust, the number of ASIC design starts essentially halvedmoving from roughly 7,750 design starts in the year 2000 to 3,623 starts in 2005.
Today the number of ASIC starts continues to decline. Some of this decline is simply due to the fact that instead of creating an ASIC (basically an IC for one specific task in one specific product) many companies are leveraging IP and all the transistors available to them via Moore's Law and are instead designing ASSPsapplication specific standard products that they can sell to many companies rather than just one.
However, ASSP starts over the same period have been relatively flat.
And if you look at analyst projections for ASIC and ASSPs design starts for the foreseeable future, most analysts project both will continue to decline. It isn't a matter of will they decline, it is how much, especially given the current downturn.
That's because fewer applications justify the cost and risks of designing and manufacturing an ASIC or even an ASSP. At every new node, manufacturing and mask costs continue to climb exponentially. A mask set for a 32-nm device is expected to be in the $30 million range. This increase in costs is speeding ASICs toward gate-array like obsolescence and is making ASSPs at each node similarly cost prohibitive.