GRENOBLE – At a time when Silicon on Insulator (SOI) technology is steadily gaining presence in today’s society, French SOI wafer manufacturer Soitec explores new domains at the substrate level in a view to offer more device solutions.
In his speech at the Minatec Crossroads in Grenoble on Tuesday (May 30), Carlos Mazure, Soitec’s CTO, addressed three points of questioning. He indeed described how wafers can contribute to the improvement of devices, assessed what can be done with engineering substrates, and finally underlined how SOI can improve devices and lead to new engineering substrates so as to allow leakage and power consumption reductions.
“The SOI technology has reached industrial maturity”, claimed Mazure in his speech, indicating that Soitec is now in 300 mm and supplies worldwide with a capacity to control wafer to wafer. “With SOI, we can now add functionalities to the substrate and have all sorts of possibilities with the materials. Here are the most promising offers for the industry.”
The creation of SOI material represents an intermediate step between the fabrication of the polished, bulk wafers and the creation of electronic components. The role of SOI is to electronically insulate a fine layer of the monocrystalline silicon from the rest of the silicon wafer. As explained by the French company based in Bernin, near Grenoble, SOI has two major advantages for integrated circuit manufacturing as it significantly increases speed (30 to 40%) and reduces power consumption (50% less power) or a combination of both. Soitec actually pioneered a viable solution that would allow chipmakers to capitalize on these advantages without investing in additional process equipment.
Moving to engineering substrates, Mazure indicated that the key drivers are the enhancement of device mobility, the reduction of parasitics, the overall IC performance as you want more features for the same cost, IC area reduction and CoO reduction.
As the industry accelerates, a real need for new features at the substrate level is becoming more visible and new areas are being explored. Among other examples are enhanced mobility with sSOI (strained Silicon On Insulator) and DSB (Direct Silicon Bond), high impedance, and as we move into the future, new materials such as GeOI (Germanium on Insulator).
Approaching substrates from 65 nm to 32 nm nodes, Mazure underlined the desired stress relations for mobility enhancement in the near future. “As you make devices smaller, the amount of material that you can bring into two gates will be limited. Another limitation stems from the risk for the layer to break”, explained Soitec’s CTO to the audience, noting that the substrate can help in this sense. “You manufacture a strained silicon layer and then you get a SOI that is strained”.
To optimize mobility, Mazure encouraged a combination of crystal orientation with an oxide in-between. “You can bond two single crystal layers, bonds under controlled rotation leading to twisted substrates. Then, you get a two dimensional stressed topology”, commented Mazure in his speech.
As a conclusion, Mazure underlined SOI ability to reduce power consumption. For future technology, there will be enhanced technology with two directions as it amplifies IC performance, on the one hand, and reduces dynamic power consumption, on the other hand. As for sSOI, he added that biaxial strain extends and amplifies device mobility enhancing techniques beyond 45 nm.