LONDON Innovative Silicon Inc. (ISi), a startup pioneer of "floating-body" memory, has come up with an improved version of the technique that provides a factor of ten improvement in the 1 to 0 margin and the data retention time. Advanced Micro Devices Inc., which took out a license for the previous generation of the Z-RAM in December 2005, has taken a license out for the second generation of the technology.
Floating body RAM is a technology for use with silicon-on-insulator processing. It does away with the capacitor used in conventional DRAM bit cells built in bulk silicon. In bulk CMOS, the charge that forms a transistor's body is tied to a fixed voltage. In SOI, the untied body is "floating" in silicon above the thick oxide layer. To make the floating body behave like a capacitor, a carefully controlled voltage is applied on both sides of the body.
For companies that start out with SOI wafers for their high-performance processors, such as AMD, IBM or Freescale, the FB-RAM approach has several advantages: fast read and write times, and a cell size smaller than embedded DRAM and about one-fifth that of a six-transistor SRAM. Serguei Okhonin, chief scientist of Innovative Silicon (Santa Clara, Calif.), declined to explain how the company had improved its floating-body technology except to say the memory was operating in "a different mode."
The improvements in performance are expected to open up Z-RAM to a broader range of applications. The second generation version is expected to scale better and is capable of 5-Mbits per square millimeter on a 65-nm process and greater than 10-Mbits per square millimeter at 45-nm. The memory is capable of up to 400-MHz clock frequency in the array when optimized for performance and the power consumption can be taken as low as 10-microwatts per megahertz when optimized for low-power consumption.
The Z-RAM Gen2 technology has been fabricated and validated as a complete memory at 90-nm, and test chips are in a number of fabs at 65-nm and 45-nm process nodes. The company has also demonstrated bitcell operation on smaller geometries and on multigate/FinFET devices and anticipates no difficulty in scaling to sub-45-nm process technologies.
"The combination of density, power, and performance coupled with its ability to work with our standard manufacturing processes makes it an extremely attractive option for use in our future microprocessors," said Craig Sander, corporate vice president of technology development at AMD, in a statement issued by Innovative Silicon.