LONDON IBM Corp. scientists have devised a way to create vacuum spaces between copper wires in semiconductors and claimed the technique -- which borrows from nature -- will lead to chips that consume less power and run faster.
IBM said Thursday (May 3) its self-assembly nanotechnology process can be incorporated into standard CMOS manufacturing lines without disrupting operations or retooling.
Intial results at IBM labs indicate that the electrical signals on chips can flow 35 percent faster, or the chips can consume 15 percent less energy compared to the most advanced chips made using conventional techniques.
IBM researchers claim this is the first demonstration of the ability to synthesize mass quantities of self-assembled polymers and integrate them into an existing manufacturing process while achieving improved yields.
IBM plans to introduce the technology into the 32-nm manufacturing process being readied at its East Fishkill, N.Y., fab that is expected to come online in 2009. Initially, it would be used for devices made for IBM's server products and later for IBM chips made for outside customers.
"By moving self-assembly from the lab to the fab, we are able to make chips that are smaller, faster and consume less power than existing materials and design architectures allow," said Dan Edelstein, IBM fellow and chief scientist of the self-assembly airgap project.
While performance and power-saving improvements are "evolutionary", Edelstain said chip design and manufacturing are "revolutionary."
He added that the patented self-assembly process moves IBM's nanotechnology manufacturing method that had shown promise in laboratories into a commercial manufacturing environment for the first time. IBM claims it will provide the equivalent of two generations of Moore's Law wiring performance improvements in a single step, using conventional manufacturing processes.