LONDON Japan's Semiconductor Technology Academic Research Center (Starc) has adopted the use of clock-tree synthesis software from Azuro Inc. (Santa Clara, Calif.) into a recommended design flow.
Starc is a semiconductor technology research and development institute established and funded by 11 of Japan's leading semiconductor manufacturers and so software recommendations from Starc can have a highly leveraged effect in terms of market penetration.
Azuro’s PowerCentric clock-tree synthesis and optimization software has been adopted for the Starcad-cel v1.5 reference design flow, Azuro said. The use of PowerCentric as able to reduce the total dynamic power consumption by 20 percent, Azuro said without disclosing what the dynamic power consumption was being compared against.
"PowerCentric was able to greatly reduce dynamic clock power by finding many more clock-gating opportunities and building much more efficient clock trees," said Nobuyuki Nishiguchi, vice president of the design methodology group at Starc, in a statement issued by Azuro. "Azuro’s results are especially impressive because they are more efficient across the board. The low-power result also achieved a better clock skew, a shorter insertion delay, and reduced total buffer area," he was also quoted saying.
Founded in 2002, Azuro is a privately held company with R&D offices in Cambridge, England.
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