NETANYA, Israel Cellot Ltd. (Netanya, Israel) is developing a programmable logic and memory architecture dubbed Field Programmable Cell Logic (FPCL), which is based on a recursive, fractal-like, structure.
Ofer Meged, Cellot's founder, president and CTO, told EE Times that the company's chip will be primarily targeted at fabs, ASIC developers and hardware developers in various areas, including space applications. "FPLC technology has been validated and tested both on the theoretical and the implementation level," said Meged, who added that the company is currently in the process of raising initial funding of $5 million.
The FPCL architecture is optimized for complex and real-time applications where the approach usually an SOC or a collection of DSPs or FPGAs, said Meged. "In my opinion, we have created a new category in the worlds of programmable devices and structured ASICs."
Meged argued that FPCL represents a small-sized programmable solution which offers a short time to market and an attractive price, and therefore the company will initially aim to serve developers, foundries and fabs.
Although some implementation work has been done the the core FPCL chip design is described as being in a pre-fab state. "We have patented our technology in Europe, the U.S and Japan, but we need the funding before we are able to go forward," said Meged.
Cellot's FPCL architecture is a collection of registered memory cells interconnected via a programmable matrix that creates a recursive hierarchical (fractal-like) structure. That means that all of the cells are similar and any number of cells may be combined to create similar larger cells. Each cell can be used for logic when memory is used as a look-up table, or as storage, or both. The matrix can route the output of each cell to the input of each cell and each I/O with a fixed and predictable delay, according to Cellot.