LONDON Greek EDA company Helic SA (Athens, Greece) is launching a bondwire layout and inductance modeling tool called VeloceWired.
The tool is said to be suitable for use designing analog and mixed-signal ICs where wire bond inductance may need to be considered as part of the overall component performance.
VeloceWired features an editor that operates as a plug-in within Virtuoso from Cadence Design Systems Inc. (San Jose, Calif.).
Bondwires are created in 2-D using a point-and-click procedure, while their 3-D properties can be edited on-the-fly. Die-to-die and stacked-die configurations are supported. Additional features include inductance annotation on the layout and persistent bondwire connectivity when moving or rotating die. A distributed netlist can be extracted in seconds, capturing complex electromagnetic effects such as self and mutual inductance, frequency-dependent resistance and capacitive coupling from wire to wire and from wire to package.
VeloceWired includes a modeling engine that can handle RLCK extraction for tens of bondwire interconnects in seconds, the company said in a statement.
"Customers using our on-chip inductance products have been asking us for a bondwire tool for some time now. So-called 'package design tools' are typically point tools foreign to the IC flow and using them in conjunction with circuit design and simulation is often tedious, error-prone and counter-productive," said Sotiris Bantas, Helic's vice president of technology in the same statement. "VeloceWired acts as an extension of custom layout and parasitics extraction and provides excellent accuracy up to several gigahertz. High-speed and RF IC designers can now afford control over the package that houses their chip, predict all applicable bondwire parasitics and optimize their design from pin to pin."
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