LONDON -- Researchers at Stanford University and the Semiconductor Research Corporation (SRC) have demonstrated, for the first time, that it is possible to produce working circuits on wafer scale based on carbon nanotubes (CNT).
Efforts to perfect CNT technology so that it can be considered an affordable and practical application in computer chips have been underway since the first CNT transistor was demonstrated ten years ago.
CNT Field-effect Transistors are considered contenders for extending current CMOS technology to create higher-level chip capability.
The Stanford research presented their advances at the 2008 Symposia on VLSI Circuits and Technology in Honolulu, Hawaii, including the demonstration of full-wafer-scale growth of directional CNTs on single-crystal quartz wafers; demoing full-wafer-scale CNT transfer from quartz wafers to silicon wafers for integration on silicon; and fabrication of logic structures that are immune to mispositioning of CNTs.
The logic structures include NAND, NOR, AND-OR-INVERT and OR-AND-INVERT on a full-wafer-scale.
"At the nanoscale, it is nearly impossible to guarantee that all carbon nanotubes will be placed at correct positions and aligned to create a functional circuit. So the question is: if we can't control these layout requirements, how can we create working circuits?" noted Betsy Weitzman, director of the Focus Centre Research Program (FCRP), a subsidiary of the SRC that funded the project.
"This exciting research has brought forward a significant breakthrough for the application of CNTs in CMOS circuits -- very efficient and effective design solutions that do not require super-precise placement of the CNTs. The Stanford researchers developed an inexpensive design flow that is compatible with CMOS processing and have demonstrated that their designs can be fabricated at VLSI scale."
According to Professor Subhasish Mitra of Stanford, this is the first time that anyone has experimentally demonstrated that it is possible to fabricate robust, imperfection-immune CNT-based circuits at full wafer-scale without paying the price of expensive defect and fault-tolerance techniques.
"The fact that these techniques are compatible with VLSI processing and have minimal impact on VLSI design flows can contribute significantly to continued advancement of Moore’s Law."
Professor Mitra's collaborators in the project at Stanford include engineering students Nishant Patil and Albert Lin, Stanford research staff member Edward Myers, and electrical engineering Professor H.-S. Philip Wong.
"Our progress potentially brings the academic and industrial communities an important step closer to the day when carbon nanotube technologies can supplement silicon CMOS technology as the technology of choice for the semiconductor industry," said Wong.
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