PARIS CEA-Leti applied research center in microelectronics claimed it has achieved a record for device matching characteristics with an AVt of about 1mV.µm, below those obtained in bulk silicon technologies, while still maintaining Ion and Ioff characteristics.
The threshold voltage variation of less than 40mV across wafer, CEA-Leti specified, is also reported for 25-nm gate length Fully Depleted SOI (FDSOI) devices using undoped channel and high-k and metal gates technology.
According to CEA-Leti, the results show that the undoped channel FDSOI device with high-k/metal gate stack is a valid alternative to reduce variability issues at 22-nm and below.
CEA-Leti said it has worked closely with STMicroelectronics NV (Geneva, Switzerland) and Soitec SA (Bernin, France) within the framework of the Medea+ Decisif (Device and circuit performance boosted through silicon material fabrication) project.
The Decisif project aims to integrate performance boosters in fully and partially depleted SOI technologies for low power and high performance applications, to validate their impact by fabricating complex 45-nm node demonstrators directly comparable with bulk Si and to develop design kits and SOI-adapted circuit design for the evaluation by application designers.