MUNICH, Germany EDA software vendor Synopsys, Inc. has announced to intensify its ties with chip vendor STMicroelectronics. The focus of the efforts centers on timing analysis and signal integrity for 45- and 32-nanometer nodes.
The companies will join forces to accelerate the development of methodologies and flows for low-power and high-performance system-on-chip (SoC) timing sign-off. The purpose of the effort is to be able to fully exploit the devices' performance potential, Synopsys said.
As part of the collaboration, ST has chosen Synopsys' PrimeTime EDA tools as the foundation for its timing analysis and sign-off methodology. The collaboration includes initiatives to accelerate and expand the development of Synopsys' portfolio of timing analysis tools to ST's globally dispersed SoC design teams, the software vendor said.
ST expects to improve its productivity by using the Synopsys tools, said ST group vice president Technology R&D Philippe Magarshack. The tools' functionality spectrum includes composite current source (CCS) modeling, statistical timing analysis and advanced signal integrity and IR-drop-based delay calculation.