"These are the fastest CPU models available and we are now making them available for free to the SystemC community to work with native TLM-2.0," said Simon Davidmann, OVP founder and chief executive officer of Imperas, in a statement.
The models support the ability to simulate CPUs at the instruction-accurate level for use in virtual platforms as a virtualized software development environment. All OVP CPU models now work with TLM-2.0 and include ARM, OpenCores OR1K, MIPS Technologies' MIPS32 4K, 24K and 34K core families and the ARC 600 and 700 families. Models and example bare metal platforms are available as open source from the OVP website, along with examples of each model being used in a SystemC TLM-2.0 platform.
Since OVP was started in March 2008, there have been close to 10,000 downloads of the software and viewings of demonstration videos and presentations. More than 500 copies of the simulator itself have been downloaded, confirming that design teams are interested in fast, free and easy-to-use virtual platforms, said Imperas.
OVP processor models in a SystemC TLM-2.0 simulation run benchmarks such as Peakspeed at between 500 and 1,000 million instructions per second.
"With TLM-2.0, OSCI has made significant strides in interoperability, enabling models from different vendors to work together in a virtual platform. In addition, features such as the Direct Memory Interface (DMI) have increased performance many times over, making TLM-2.0 a viable option for software virtual platforms," Davidmann said.
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