LONDON Market research company Frost & Sullivan has written a document in praise of BeSang Inc. (Beaverton, Oregon) a fabless semiconductor company, founded in 2003 with strong Korean connections that is developing a 3-D integrated circuit technology.
BeSang has demonstrated a fully functioning single-chip 3-D IC in 0.18-micron technology on a 200-mm wafer recently.
"From a benefit perspective, Besang's 3-D IC solution has got clear-cut winning edges when compared to both conventional 3D packaging technologies and TSV-based [through-silicon via] 3-D IC technologies," the research firm said in its note.
BeSang's proprietary single-chip 3D IC technology enables the development of higher density memory arrays using vertically oriented transistors. One of the cited benefits of BeSang's 3D IC technology is that it can be cost-effectively implemented in existing CMOS facilities without significant modification of existing equipment or process flows.
The technology also can be used to produce low-cost stand-alone memories (volatile or nonvolatile) and high-performance embedded memories for system-on-a-chip (SoC), central processing unit (CPU), digital signal processor (DSP), and application-specific integrated circuits (ASIC) by separating embedded memories from neighboring logic circuits and fabricating the memories on top of the logics with the 3D technologies.
F&S point out that the technology is different from conventional package level 3-D integration. The single-chip 3D IC technology transfers thin single crystalline silicon on top of first substrate and then builds device layers in it.
"Primarily, the cost and size of the die is significantly low when compared to the competing 3-D counterparts. Dramatic reductions in die size have been achieved because the devices are now implemented in two or more layers and through the reduction of memory cell size. Secondly, the ability to offer unrestricted 3-D interconnects enables the development of high-speed 3-D devices. Conventional 3D packaged devices have limited interconnects between top and bottom circuits because they require precise wafer alignment, large landing pads, and TSV. In general, the number of interconnects is less than 1000 per chip, which is insufficient for high-speed 3-D IC operations," F&S said.
For BeSang’s 3-D ICs, there is no restriction of number of 3-D interconnects because the donor wafer is not patterned before wafer bonding and 3-D interconnects are implemented using conventional vias. Hence, millions of interconnects can be implemented.
"With this solution, the industry will no longer need to rely on reducing device dimensions for achieving miniaturization, which requires huge investment in expensive lithography tools. It will get freedom to build higher density IC chips by simply adding more layers in 3D directions in a cost-effective manner. With around six granted patents and 20 patents pending around this technology, BeSang Inc. single chip 3D IC solution is poised to carry 3D integration forward toward numerous applications that can be commercialized," Frost & Sullivan concluded.
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