LONDON Hardware-software co-verification specialist Emulation and Verification Engineering SA (EVE) has added support for SystemVerilog Assertions, flexible probes, and complete access to all combinational signals at run-time, to its ZeBu (Zero Bugs) emulation systems.
The extensions come through the use of EVE's recently unveiled zFAST (ZeBu FAst SynThesis) tool.
In January, EVE announced that it will offer synthesis capabilities to handle large designs with a bottom-up and top-down approach targeting its ZeBu emulation systems.
EVE (Palaiseau, France) says SystemVerilog Assertions improve the debugging process by accelerating the location of bugs and by minimizing the size of waveform files needed to isolate the bug.
Synthesizable assertions can be compiled into the emulator with a scope at the design, module, instance and assertion level. Assertion failures, starts and ends, and successes can be reported live or via post-processing in any mode of operation for every assertion in the register transfer level (RTL) code.
Added during design compilation, the maximum number for flexible probes is higher ó more than 30,000 per field programmable gate array (FPGA) ó than for static probes.
EVE suggests flexible probes do not affect emulation performance when they are disabled.
But when enabled, they generate signal waveform files at the maximum speed offered by the fastest host PC hard disk without limiting the number of cycles or stopping the emulator. Because flexible probes are fully integrated into zRun and the ZeBu C++/C application programming interface (API), system-on-chip (SoC) designers can use them in any mode of operation.
Enhanced dynamic probes are integrated into the ZeBu run-time environment to generate a single waveform file and can be accessed interchangeably by software test benches, providing improved debug capabilities.
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