LONDON Research institute IMEC (Leuven, Belgium) has transferred an EDA tool for variability-aware modeling (VAM) of memories to Samsung Electronics Co. Ltd. The tool predicts yield loss of SRAMs caused by the process variations of deep-submicron manufacturing processes.
MemoryVAM helps avoid design weak spots and other reasons for tape-out failure, IMEC claimed. The tool also helps estimate yield loss due to changes in cycle time, access time and static and dynamic power consumption caused by process variations, the institute said.
MemoryVAM is part of IMEC’s Variability Aware Modeling (VAM) flow, which IMEC claims is capable of percolating process variations from the process technology up to the system-on-chip (SoC) level.
The method requires three inputs. The first is a transistor-level netlist description of a segment of the memory describing all circuitry involved from input to output. The second one is a set of parameters describing the internal architecture of the memory, thus how the memory is built from the segment information, including redundancy and error correction code infrastructure. The third one is information about the variability of the devices and interconnects used in the underlying technology. This information can be provided in either the form of statistical distributions of certain transistor parameters, scattered data obtained via statistical simulation of the device or just plain data set obtained via silicon measurements.
The power of MemoryVAM lies in the analysis of parameters of the memory that can be directly embedded in the input netlist by the designer. These are then used to carry out the implementation of the method, without requiring additional custom modeling steps from the user. The key to this strategy is the ability to complement the analysis of a nominal memory model under test with statistically sampled variants of the devices. This is done by using an in-house developed statistically enhanced Monte Carlo technique, although it also allows the usage of any other available enhanced sampling technique. With this analytical technique, statistical information on the critical path percolates to the SRAM organization level, resulting in a realistic prediction of the yield as perceived by the memory tester and/or equivalent BIST (built-in-self-testing) technique.
"With MemoryVAM IMEC completes a missing steppingstone in industrial and academic state-of-the-art design-for-manufacturing flows which lacked such modeling capabilities for memories," said Rudy Lauwereins, vice president of the Smart Systems Technology Office at IMEC, in a statement. "This is especially interesting for embedded SRAMs, which are considered to be the most sensitive component to process variations of today's systems-on-chip."
"We expect that MemoryVAM will be helpful for parametric yield modeling of embedded SRAM design and for understanding the unknown gap between design and silicon results due to process variability in deep sub-micron technology below 45-nm," said Kyu-Myung Choi, vice president of the design technology team at Samsung, in the same statement.
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