LONDON Arteris Inc. (San Jose, Calif.), a supplier of networking-on-chip intellectual property, has said that it has worked with Duolog Technologies Ltd. (Dublin, Ireland) to integrate Duolog design tools with Arteris' NoC tools and IP to streamline the integration of semiconductor IP blocks on an integrated circuit.
The collaboration makes use of Duolog's Socrates chip integration platform, a suite of tools for capturing, viewing and validating various elements of the infrastructure of complex systems chips. It also uses the Arteris NoC compiler tool. NoC compiler generates an IP-XACT description which includes high-level interfaces, ports and memory map data.
The Duolog system uses the IP-XACT description to allow designers to capture the software view of the system from low-level IP registers and bitfields to the full system-level memory map. The Socrates Bitwise register management tool captures the memory map infrastructure. It generates a wide range of collateral including documentation, hardware design and verification infrastructures and software API models. The streamlined flow also incorporates Duolog's Socrates Weaver software, a rules-based assembly engine that enables interface and port-level connectivity.
"The integration of our NoC generation system with Duolog's viewing and validation capabilities provides a robust and efficient way to integrate complex SoCs," said Charlie Janac, CEO of Arteris, in a statement.