PARIS French SOI specialist Soitec SA claimed its 300mm ultra-thin SOI (UTSOI) wafer platform supports fully depleted device (FD) applications at the 22-nm node and beyond.
Soitec (Bernin, France) said it is able to manufacture SOI with extremely thin top-layer silicon (20nm) to a thickness uniformity tolerance of Ī5 Å (angstroms) in high volume with high yields.
The specific parameters of the final SOI substrate, the company added, can be tailored to customer applications, and manufactured with the same yields and similar costs as the current generation of mainstream SOI wafers.
At Semicon West last year, Soitec announced that it had qualified SOI wafers with ultrathin buried oxide (BOX) and silicon layers. The SOI wafers, dubbed XUT+ to describe the ultrathin top silicon and BOX layers, are aimed at both partially depleted (PD) and fully depleted devices, including multi-gate transistor architectures, such as finFET and trigate, that may play a role at 22nm and beyond.
"UTSOI provides a solid foundation for planar and ultra-thin body devices, giving designers the ability to drastically cut power consumption and leakage while preserving performance. It simplifies the overall CMOS architecture, thus reducing the cost of ownership below a bulk approach," commented Paul Boudre, COO of the Soitec Group. "We are fully prepared to support our partners in fine tuning their manufacturing process steps to meet ultra uniformity requirements, and deliver maximum value from this ultra-thin layer advantage."