Renesas Technology Europe has announced its SiP Top-Down Design Environment to boost efficiency when developing system in package (SiP) products combining multiple chips, such as system on chip (SoC) devices, MCUs, and memories, in a single package. It uses a top-down (predictive) design approach in which key characteristics, such as design quality and heat dispersion, are verified during the initial design stage.
Since an SiP combines multiple chips in a single package, the design of the package substrate configuration and wiring are more complex than is the case for a single-chip SoC device. In addition, signal integrity between the multiple chips and adequate heat dispersion have both become very important because of increased memory speed and capacity, and the accompanying higher power consumption and heat generation density. To achieve quicker SiP development it is therefore critical to ensure signal integrity and to make verification of heat dispersion performance as efficient as possible.
The newly developed SiP Top-Down Design Environment replaces the conventional back annotation (analytical) design methodology, in which these characteristics are analyzed at a late stage of the SiP design process, with a top-down design methodology, in which verification is done in the initial SiP design stage.
In an SiP in which multiple chips are arranged in a stack, the chips and the package substrate are connected by wires. In the past, the analysis of electrical and thermal characteristics was independent of the wire bonding design and package substrate wiring design processes. As a result, it was necessary to update the substrate data manually for each tool used in chip and wiring analysis.
The new design environment uses an integrated design database to provide unified management of design data and easy connections for analysis of electrical or heat dissipation characteristics. Thus, data on chip shapes and positions as well as chip-to-chip connection data can be extracted from the database and connected to the substrate layout tool. In turn, wire bonding and substrate pattern data from the substrate layout tool can be connected to other analysis tools. For enhanced ease of use, a common interface is provided for running the tools and making settings.
Analysis of the electrical characteristics of a large-scale package substrate previously involved division of the area to be analyzed into several sub-areas in order to complete the analysis in a practical amount of time. Since the manner in which the area to be analyzed is divided can affect the accuracy of the analysis, careful consideration had to be given to the division method itself. The circuit simulations also involved complex combinations of analysis conditions, such as SoC drive adjustment. As a result, building the simulation environment and determining the execution results was a very time consuming process, and it was difficult to estimate noise characteristics at the initial design stage.
The new design environment includes an electromagnetic field analysis tool that supports large-scale substrates. This means it is not necessary to divide up the area to be analyzed. In addition, simulation condition setting and result determination for circuit simulations are automated. It is therefore possible to estimate noise at the initial design stage based on the electrical characteristics.
Further, package models for evaluation of heat dispersion characteristics have until now been created manually by referring to the substrate layout data. As a result, the development of package models for heat dispersion evaluation has been time consuming with limited accuracy for the resulting models.
The new design environment extracts from the substrate layout data information on the conductor pattern area share (remaining copper ratio), layer thickness, and materials of the internal SiP package wiring, power plane, etc., the number of via holes between layers, and the shapes and positions of the chips, and it automatically builds an environment for the heat dispersion evaluation package model. Another newly developed function applies the power consumption distribution of the SoC to the thermal analysis model so that the distribution of heat generation within the chips is taken into account. These advances not only increase the accuracy of the models, they make it possible to complete the thermal analysis in a short amount of time.
Renesas Technology plans to expand the application of the SiP Top-Down Design Environment to the development of a broad range of SiP products and will continue to build development solutions that respond to evolving customer requirements.
About Renesas Technology Corp.
Renesas Technology Corp. is the world’s No.1 supplier of microcontrollers and one of the world’s leading semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets. It is also a leading provider of Power MOSFETs, Smart Card microcontrollers, RF-ICs, High Power Amplifiers, Mixed Signal ICs, System-on-Chip (SoC), System-in-Package (SiP) and more. Established in 2003 as a joint venture between Hitachi, Ltd. (TSE:6501, NYSE:HIT) and Mitsubishi Electric Corporation (TSE:6503), Renesas Technology achieved consolidated revenue of 702.7 billion JPY in FY2008 (end of March 2009). Renesas Technology is based in Tokyo, Japan and has a global network of manufacturing, design and sales operations in 16 countries with 25,000 employees worldwide.
For further information, please visit http://www.renesas.com
Headquartered in Buckinghamshire, UK, Renesas Technology Europe has offices in Denmark, Finland, France, Germany (3 offices), Italy, Spain, Sweden, and representation via related companies in the Czech Republic, South Africa and Russia.
In Europe, Renesas focuses on automotive (control, networking, infotainment), wireless (GSM, CDMA and Bluetooth), smart card and microcontroller applications such as white goods, motor control, metering, energy management, building security and healthcare. It employs over 150 engineers to develop solutions for the European market and to assist customers with application development. Renesas is a leading supplier of smart card ICs in Europe. Europe is the world’s largest market for automotive electronics and microcontrollers, and is the region of most design influence for wireless electronic products. Feedback from customers in Europe has great influence on Renesas’ product development.
For Europe visit http://www.renesas.eu
Company contact for reader and customer inquiries:
Renesas Technology Europe GmbH, Karl-Hammerschmidt-Str. 42, 85609 Aschheim-Dornach
Tel.: +49 89 380 70-216
Fax: +49 89 380 70-273
Note: The above text is the public part of the press release obtained from the manufacturer (with minor modifications). EETimes Europe cannot be held responsible for the claims and statements made by the manufacturer. The text is intended as a supplement to the new product presentations in EETimes Europe magazine.