MUNICH, Germany At the Design Automation Conference (DAC) that currently takes place in San Francisco, a group of researchers and chip designers from the Dresden Technical University present what they hope it could offer a solution for the challenge of modem signal processing for upcoming wireless communications generations.
With the chip baptized Tomahawk, the scientists from TU Dresden's Vodafone chair intend to address challenges posed by upcoming cellular standards such as 3GPP, LTE and WiMAX. Applications associated to these standards such as broadband media applications yield the requirements for data-dependent control flow which in turn calls for quick reconfigurability and flexible scheduling, combined with high computational demand.
In order to meet these demands, the heterogeneous MPSoC (Multi-Processor System on Chip) introduced embraces two Tensilica Xtensa control processors, eight vector fixed-point DSPs and two scalar floating-point DSPs on a 10 mm by 10mm die. The key component of the device however is the CoreManager, a dedicated hardware scheduler.
In contrast to existing multicore solutions, the Tomahawk is easy to program, claimed professor Gerhard Fettweis who manages the Vodafone chair, in an EE Times Europe interview. At the same time, the chip design which embraces some 60 million transistors, is very power efficient, Fettweis explained. "This device proves that we can get the power consumption lower by a factor of ten compared to today's low energy concepts provided by Qualcomm, Ericsson and the like," the mobile communications expert said.
The challenges associated with the design of such a complex hardware-software continuum are about to trigger major efforts to develop adequate design tools in the EDA industry, Fettweis claimed. The device has been designed using a proprietary Synchronous Transfer Architecture design template.
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