PARIS European chipmaker STMicroelectronics NV said it has selected integration signoff solutions from Cadence Design Systems, Inc., including QRC Extraction and Encounter Timing System, for 65- to 32-nm design. It is qualifying the system for 32-nm process technologies.
Commenting on its choice, STMicroelectronics said the Cadence integrated signoff suite delivers advantages in runtime and accuracy. It also delivers a seamless integration of all the analysis components in a single cockpit, and with the complete Encounter implementation design flow.
This approach to integrated signoff, Cadence claimed, provides fast convergence, predictable design closure, and completely scalable multi-CPU backplane to enable overall cycle time reduction.
"At 65- to 45-nanometer process nodes, signoff solutions need to deliver accurate silicon predictability, high performance and integration with digital implementation flows to meet our time-to-market," commented Philippe Magarshack, group vice president and general manager, Central CAD and Design Solutions, Technology R&D, at STMicroelectronics.
He continued: "Cadence's signoff combination of QRC Extraction and Encounter Timing solution demonstrated excellent design convergence which met our stringent accuracy specifications for our complex designs. This gave us the confidence to further extend qualification to our most advanced 32-nanometer projects."