LONDON IBM Corp. (East Fishkill, N.Y.) said it has made a 32-nanometer, silicon-on-insulator (SOI) embedded DRAM test chip and claimed it is the semiconductor industry's smallest, densest and fastest on-chip dynamic memory.
The use of SOI produces a 30 percent chip performance improvement and 40 percent power reduction, compared to standard bulk silicon technology IBM said. It also means that embedded DRAM, which only requires a single transistor per memory cell, offers density, speed and capacity better than conventional on-chip static random access memory (SRAM) announced in 32- and 22-nm technology.
The IBM eDRAM in 32-nm SOI technology achieves latency and cycle times of less than 2 nanoseconds. In addition, the IBM eDRAM uses four times less standby power and has up to a thousand times lower soft-error rate, offering better power savings and reliability compared to a similar SRAM.
Embedded memory is a key performance enabler for multicore processors and other integrated circuits, IBM asserted. The prototype has implications for server, printer, storage and networking applications. In mobile, consumer and game applications, it can result in a smaller system form-factor, lower-cost and energy savings.
IBM intends to bring the benefits of its 32-nanometer SOI technology to a wide range of application-specific integrated circuit (ASIC) and foundry clients and will use the technology in chips for its servers.
IBM already is engaged with early access foundry clients in 32-nm technology and ARM is developing design libraries for the technology. An initial 32-nm ARM library is available now and IBM has extended this collaboration to include 22-nm SOI technology, enabling ARM to gain early access to this technology. This represents the two companies' commitment to align early on process technology, design rules, design library and cores for next-generation SOI technology.
"We are making this 32-nm offering available to clients who are ready to benefit from the significant performance and power advantages of this seventh generation of IBM SOI technology," said Gary Patton, vice president for IBM's semiconductor research and development center. "The industry-leading, dense embedded memory and our design library agreement with ARM, underscore our ability to provide clients with a market edge and a clear progression path to 32-nm and 22-nm SOI technology nodes."
IBM engineers plan to describe the 32- and 22-nm eDRAM technology at the International Electron Devices Meeting in December.
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