PARIS Rambus announced its Mobile XDR memory architecture for next-generation mobile products, combining high-bandwidth and low-power.
The Mobile XDR memory architecture will enable future mobile memory platforms which can achieve throughputs of up to 4.3Gbps per pin while being power efficient.
With this breakthrough performance, SoC platforms can achieve over 17GB/s of memory bandwidth from a single Mobile XDR DRAM device while extending the battery life of many mobile products by more than 30 minutes, when operating under the most power-hungry usage profiles.
†The Mobile XDR architecture enables significant cost savings for SoC chips by offering pin-count reduction and a smaller interface. Power reduction is achieved through an aggressive decrease in active power coupled with fast transition times to power-saving modes.
This enables system designers to minimize memory subsystem power to increase battery life across a wide range of applications from simple voice transmission to demanding multimedia such as stereoscopic 3D HD video.
The Mobile XDR memory architecture uses key innovations from Rambus' Mobile Memory Initiative.
This includes the very low-swing differential signaling (VLSD): a bi-directional, ground-referenced, differential signalling technology, the FlexClocking architecture which uses asymmetric partitioning and places critical calibration and timing circuitry in the SoC interface, greatly simplifying the design of the DRAM interface, and Advanced Power State Management (APSM) to reduce memory system power and provide ultra-fast transition times between various low-power and active operating modes.
In addition, Rambus' FlexPhase and Microthreading technologies help enable the superior power efficiency of the Mobile XDR architecture. Key components of the Mobile XDR memory architecture include Mobile XDR DRAM, Mobile XDR memory controller PHY (MIO), and the Mobile XDR memory controller (MXC). The Mobile XDR memory architecture is currently available for licensing.
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