HyperTransport is becoming one of the most popular links for chip-to-chip communication. It offers a flexible interconnect architecture that is designed to reduce the number of busses within the system by allowing speed scalability to fit many application needs. This technology has been adopted in applications ranging from embedded systems, to personal computers and servers, to network equipment and supercomputers. As HyperTransport continues to appear in more and more platforms, system engineers are requiring sophisticated debug tools to aid in validation. In most cases, engineers select a logic analyzer as their debug tool of choice. Logic analyzers provide acquisition of deep records and advanced triggering capability to pinpoint specific events on the bus. One of the biggest challenges facing engineers as they try to debug HyperTransport links is making the physical connection between their logic analyzer and the target system.
HyperTransport lanes are currently capable of operating up to 2.4Gb/s. At these speeds, the logic analyzer probing connection can be the critical link to making a successful measurement. Factors such as the probe's electrical load can break the system such that errors occur in the HyperTransport protocol solely due to the probe. In addition, the stub length of the probing interconnect can limit the speed at which the logic analyzer can successfully acquire the HyperTransport data due to signal distortion at the probe tip. These factors have put an emphasis on moving toward advanced probing technology.
Historically, the connection between the logic analyzer and the target signal was made through a standard connector. The connector served as the electrical and mechanical connection to the target signal. The physical size of the connector itself limited its performance due to the relatively large electrical length of the stub between the target signal and the probe tip circuitry residing in the probe. Connector-based probing systems are capable of successfully acquiring data up to 400Mb/s with an equivalent capacitive loading of 1.5pF.
As HyperTransport data rates moved into the multi-Gigabit range, the connector-based probing system was insufficient. Connectorless probing was adopted as the solution to this problem. Connector-less probing eliminates the connector by using a compression spring-pin interconnect. The spring-pin interconnect makes a direct connection to surface mount pads on the target signal. This has the effect of reducing the stub length between the target signal and the probe tip circuitry by shrinking the physical size of the interconnect structure. This new style of probing interconnect has allowed logic analyzers to successfully acquire HyperTransport data up to 2.4Gb/s with an equivalent capacitive loading on the target as low as 450fF.
Figure 1: FuturePlus Systems has adopted soft touch probing from Agilent Technologies to enable HyperTransport analysis at 2.4Gb/s.
Connector-based probing has been sufficient for the majority of HyperTransport debug applications. However, as data rates of HyperTransport move above 2Gb/s, the electrical parasitics of the connector itself will limit the data rate that the target and the analyzer can achieve. The main limitation of connector-based probing is the electrical length that exists between the target signal and the probe tip circuitry. This electrical length mainly consists of the connector structure itself. This length presents an unwanted electrical stub. Since the connector serves as both the electrical and mechanical connection to the target, it must be a relatively large structure to provide mechanical robustness. This electrical stub presents loading on the target signal. In addition, the stub that the target signal must traverse to reach the probe tip circuitry will distort the signal that the analyzer sees. This directly affects the measurement capability of the analyzer since it is not observing a signal that is representative of the actual target signal. The connector stub itself will dictate the loading on the target and the maximum datarate that the analyzer can achieve. Current HyperTransport analysis probes using connector-based interconnect are capable of achieving up to 400Mb/s.
Figure 2: The FS2241 connector-based HyperTransport probe from FuturePlus Systems can achieve data rates up to 400Mb/s. The main limitation comes from the physical size of the connector-based interconnect.
The most recent advance in HyperTransport probing is the application of soft touch connector-less probing technology from Agilent Technologies. In connector-less probing, the HyperTransport lanes are routed through small surface mount pads (SMT) on the target. A mechanical retention module is hand soldered to the target PCB using four through-hole pins. The retention module aligns and compresses the soft touch spring-pin onto the SMT pads making the electrical connection. Since the electrical connection (spring-pin) and mechanical connection (retention module) are decoupled, this allows a much smaller electrical interconnect to be used. By doing this, the tip resistor of the probe circuit can reside physically closer to the target being probed (Figure 3). This reduces the electrical stub length between the target signal and the tip resistor, thus reducing parasitic loading on the target and improving the signal quality that the probe observes. Both of these factors lead to increased performance of the HyperTransport analysis probe.
Figure 3: Using the FS2243 connector-less HyperTransport probe (bottom) the tip resistor of the probe circuit can reside physically closer to the target being probed compared to the FS2241 (top).
In both the connector-based and the connector-less probes, the tip resistor value is the same (226 ohms). The only difference between the probes is the electrical stub present due to the interconnect. This interconnect possess parasitic capacitance and inductance that will load the target and degrade the performance of the analysis probe. Figure 4 plots the input impedance of the FS2441 connector-based HyperTransport probe versus the FS2443, which uses soft touch probing technology. From this model, the equivalent parasitic capacitance of each probe can be determined. The connector-based probe acts like a 1.5pF capacitor to ground when connected to a HyperTransport signal. The connectorless probe acts like a 450fF capacitor to ground. By moving toward the soft touch probing interconnect, the capacitive load on the target is reduced by over 300%. This plot also illustrates the effect of the parasitic inductance in the interconnect. The parasitic inductance and capacitance will form a resonance that will prevent the target signal from entering the probe. At this frequency, the analysis probe stops observing the signal and its input impedance begins to increase. In the case of the connector-based probe, this occurs at 3.5GHz. This is a problem for data rates above 2.3Gb/s because the third harmonic of the target signal is not observed by the probe. This leads to decreased performance of the analysis probe. In the connectorless probe, the resonant frequency is above 6GHz, which has no effect on HyperTransport links running at 2.4Gb/s.
Figure 4: The input impedance plot of the two probe styles illustrates the advantages of soft touch connectorless probing on HyperTransport debug.
Soft touch spring-pin technology has a host of mechanical advantages as well. The micro spring-pin has a patented four-point crown tip that pierces oxidation and contamination on the target pads. This allows the spring-pin to work across all standard PCB finishes such as organic coat and HASL. Expensive processes, such as gold plating, are not required to ensure the mechanical connection. In addition, no cleaning processes are needed to remove contamination. This is a significant improvement over other compression interconnect such as elastomer or C-springs which require special finishes and a cleaning process to prepare the target pads.
In addition, each soft touch interconnect is an individual spring-pin. This allows increased compliance in the interconnect. The spring-pins are able to accommodate up to 0.030-inch of compliance from spring-pin to spring-pin which guarantees a robust electrical connection on non-planar surfaces. Non-planar surfaces typically result from PCBs with low layer counts. Commodity motherboards typically use 4-layer PCBs to reduce cost. Since HyperTransport is specifically designed for computing systems, the analysis probe must be able to work in non-planar environments without special consideration. The soft touch technology uses the same footprint and retention module in all applications. No special consideration is needed to guarantee planarity on the target. Other compression interconnects such as elastomer or C-springs require extra stiffening plates to be placed on the backside of the probing footprint to guarantee planarity. Since these styles of compression interconnect have much less compliance (>0.006-inch), the burden is on the user to provide a planar surface.
Figure 4: Soft touch spring-pin technology offers superior mechanical robustness over connector-based probes. While connectors typically guarantee connectivity in the range of 50-100 insertions, the soft touch interconnect has been qualified to at least 500 cycles.
As HyperTransport adoption in computer systems continues to increase, digital system designers will turn to the logic analyzer as their main debug tool. In order to take advantage of the full measurement capability of the logic analyzer, the physical connection to the HyperTransport link must be chosen carefully. Until recently, connector-based HyperTransport probes have been successful in meeting the needs of engineers. However, as HyperTransport enters into the multi-gigabit era, new probing technology is needed. By using the soft touch probing, FuturePlus System has succeeded in creating an analysis probe capable of capturing HyperTransport at 2.4Gb/s. This advance in probing technology has enabled engineers to successfully and quickly debug HyperTransport links with confidence in their probing connection.
About the Author
Brock J. LaMeres received his Ph.D. from the University of Colorado in 2005 where his research focus was noise reduction techniques in high-speed interconnect. He is currently a hardware design engineer for Agilent Technologies in Colorado Springs where he designs logic analyzer probes and high-speed transport systems. LaMeres has published over 30 papers in the area of signal integrity, holds 1 patent in the field of electronic probing, and is a registered Professional Engineer in the state of Colorado.