Market demands are continually pushing semiconductor developers to design smaller, faster chips that consume less power. As the demand for bandwidth increases, developers are faced with additional design challenges, such as managing noise, process sensitivity, testability, signal integrity, and skew (the difference in channel delay between measurement channels). Skew, in particular, has severe effects on the performance of a chip's multi-lane interface, limiting its maximum length for a given bandwidth.
Traditionally, the approach used to address skew has relied on passive techniques that involve carefully matching/balancing the delays of each data path of the interface. However, as the bandwidth of multi-lane interfaces increases, this approach becomes ineffective. Hence, to tackle the issue of skew, more complex/dynamic techniques are required. Generally, these solutions are based on analog designs and techniques that carry a costly penalty in both power dissipation and size. New digital design approaches have been shown to offer superior performance not only with these specific additional challenges, but also in overall terms of reduced area and power requirements as compared with equivalent analog solutions.
This article will address the drivers in the market creating the demand for these smaller, faster, less power-intensive interfaces, the challenges in designing them, and the advantages of digital design techniques in the implementation of these new high-performance interfaces.
Faster, smaller, less power-hungry: these attributes represent the consistent mantra for semiconductor developers in their quest for improved chip and interface design. The rankings of these features have sometimes traded places over the past few years. In the late 90's, speed was the key driver of innovation at the high-performance end of the market (such as servers and routers), as chip and system designers sought to keep up with the forecast boom in bandwidth demand and hardware innovation. Consumer and corporate adoption of broadband was forecast to double on a yearly basis, and network processor startups seemed to be springing up on every Silicon Valley corner. Power and area only came into importance due to increasing packaging costs for large die and the ability to effectively dissipate the power these devices consumed.
At the same time, at the other end of the market were handheld devices such as PDAs and cellular phones. In these product categories speed still had its place, but was not as important as area and power. The devices had to be small enough to fit into a handset. And even if power dissipation could be effectively handled, battery life was a crucial issue, making power the key attribute.
In the current economic downturn, the emphasis is on system economics and, as a result, speed, power and area all must be optimized to provide the best system efficiency. To achieve further gains in power and area usage, many of the major players in the industry (Intel, IBM, Texas Instruments, and AMD) are pushing towards 90nm production (ironically while 0.13µm processes still struggle with stability). And this year's Design Automation Conference in Anaheim will devote a full-day tutorial to Design Techniques for Power Reduction.
Speed still maintains a stand-alone appeal. Scientists at Stanford's Linear Accelerator Center recently smashed the Internet speed record, transferring data at 923 Mb/s for nearly a minute, a rate 3500 times faster than a typical Internet broadband connection. This level of data rate could make a reality of video-on-demand if there were computers capable of handling such loads. "You have this inversion where the limitations of advances will not be the speed of the Internet, but rather the speed of your computer," commented Harvey Newman, of the California Institute of Technology.
Research like this shows that while advancements in pure bandwidth capability are not currently at the top of the list, they will clearly reassert themselves sometime in the not-to-distant future. The bottom-line is that designers will welcome a technique that can provide improvements in any of these traits. A digital design approach has been shown to provide speed equivalent or better than competitive analog solutions, and significant improvements in size and power usage.
In general, in the analog realm, creating faster chips and interfaces requires increased area. But as data transfer speeds increase, additional challenges present themselves, each of which have their own impact on power and area requirements. To understand these new challenges in creating smaller, faster, less power-hungry interface designs, we need to look at the effects of speed on the bits of data.
As the speed of the data transfer increases, the amount of time that a particular bit remains valid (known as a "unit interval" or "bit-time") decreases. At gigabit speeds, the amount of skew that exists between any two lanes becomes proportional to the bit-time of the data being transferred. Furthermore, the amount of skew that exists between the lanes of the interface is largely unknown. Hence, when data is received at the destination node, the bits are no longer "word-aligned" as when they were transmitted, preventing the use of a simple register to receive the data.
To solve this, interfaces such as the PCI-Express variant of the peripheral component interface (PCI), XAUI (the 10-gigabit variant of the Attachment Unit Interface), and the serial peripheral interface (SPI) standards make use of serializer/deserializers (SerDes) to transfer the data and "re-collate" or "word align" at the destination. Typically, the SerDes are analog based designs, employing phase-locked loops (PLLs) or delay locked loops (DLLs) (Figure 1).
Figure 1: Layout for a basic PLL, which consists of the phase-detector (PD), Low Pass Filter (LPF), Voltage Controlled Oscillator (VCO), and feedback network (H(s))
The challenge now becomes implementing a large number of PLL/DLL blocks for a multi-gigabit interface that is in very close proximity to high-speed digital circuit blocks. This challenge manifests itself in a number of ways.
Electrical noise in electronic systems can be classified as device/component noise and man-made noise, the latter of which is generally coupled or conducted into a circuit from external sources. While electrical noise appears in both analog and digital systems, its effects on each are different. For small-signal circuits in analog systems, noise is a major concern because the desired signal and the noise signal are processed identically, which creates the potential for corrupted data. Hence, it is highly preferable to maintain a large signal-to-noise ratio.
In the implementation of an analog circuit such as a PLL or DLL, conducted noise is always an issue. In particular, when placing multiple PLL and DLL blocks in close proximity to digital blocks (or to each other), careful attention must be paid to conducted noise between the various blocks. Supply rail noise, often generated by switching logic, I/O circuits, or other PLL and DLL blocks is another form of conducted noise that must be addressed.
In digital circuits, electrical noise usually results in timing variation (in other words, jitter or push-out), and the extent is highly dependent on the amount of noise present and the noise margin of the particular technology. In a binary circuit, recognition of a signal as either a logic 0 or logic 1 depends on whether its voltage is above or below a given set of thresholds (Figure 2). It is the values of these threshold voltages that determine the noise margin and the amount of noise that can be tolerated by the system.
Figure 2: The noise margin of a digital signal is set by the upper and lower threshold voltage values. Note, the switching point for most CMOS gates occors naturally at 0.5Vdd.
Power (and Area)
In analog systems, a significant percentage of the power is dissipated in the biasing networks (which draw a DC current whether the circuit is active or not). In addition, biasing networks have an additional area penalty that increases if a process-voltage-temperature (PVT) compensation circuit is required.
For most of the digital technologies in use today, the transistors are designed to operate as a switch residing in either saturation (fully-on) or cutoff (fully-off or high impedance) mode. While operating in either of these states, the amount of power dissipated is significantly less than for devices operating in the linear region. Hence the majority of the power dissipated in digital circuits occurs at the moments when they are transitioning from one state to the other.
Each semiconductor process and geometry has a set of characteristicssuch as supply voltage resistance, capacitance, transistor gain, and leakage currentsthat determine the performance of analog and digital circuits alike. Digital circuits and systems are generally more tolerant of processes changes, due to the fact that their transistor operates as a switch.
Conversely, analog circuits are very sensitive to all of the above mentioned process characteristics. For PLL or DLL designs, process has a significant effect on key sub-circuits. In the case of the PLL, these are the low-pass filter (LPF) and voltage controlled oscillator (VCO). As an example, the reduced supply voltage and increased leakage current of the 130nm and 90nm processes require a re-design of PLL/DLL taken from previous process designs to account for the performance and operational shifts. In this case, to achieve the desired performance generally requires an increase of the bandwidth gain of circuits, which translates into larger devices and circuit area.
Testability and System Debug
Testability is a key issue for designers of both analog and digital circuits. The ease of testing analog systems is highly dependent on the application and the type of analog system. For some analog circuits, such as PLL and DLL blocks, system bring-up and testability becomes problematic with both the application and its target operation. PLLs and DLLs generally don't lend themselves to common debugging techniques, such as reducing the operating frequency. Hence, work-around strategies and/or circuits must be included for this purpose, further impacting size and power usage.
In contrast, digital designs, by nature, offer inherent testability, including bring-up strategies such as SCAN, reduced clock frequency and single-step procedures. Although not all of these strategies are applicable to all digital circuits and architectures there is usually a minimum set that provide adequate test coverage.
Skew Management Strategies
In addition to the challenges described above, a final hurdle for high-speed SerDes products to overcome is the effect of skew. Analog and digital designers approach this problem in significantly different ways.
An analog approach employs two fundamental strategies for handling skew in SerDes-based multi-lane interfaces. In both schemes, "phase-correction" is performed first, to properly sample the data stream. Once this has been accomplished, a training pattern is transmitted over all lanes. This pattern is used to correlate recovered data to the proper "known" word alignment.
In the first strategy, each individual lane is handled as an independent serial link. At the source node, parallel data is serialized and a clock signal encoded before it is transmitted over each lane. A clock data recovery (CDR) block is used on each lane at the destination to recover the data stream. The second strategy serializes data at the source node, then transmits the data stream over each lane. A DLL is placed on each lane to zero out the delay and establish a common sampling point across all lanes of the interface. A common link clock can then be used to load the recovered data into a first-in, first-out (FIFO) circuit.
Instead of digitally mimicking an analog process, a new approach accomplishes de-skewing entirely within the digital domain. During a training sequence the training pattern signal is sampled to find threshold-crossings (distinguish 1s from 0s). Hence, the relative time delay and/or phase information for each signal line is measured digitally. To properly phase-align the data streams, additional delay is added to "early" signals to bring them into alignment with the "latest" signal line.
This is accomplished by piping these signals through extra logic gates via a digital delay-line (Figure 3), to bring them into time-alignment with the "late" signal line. Once phase alignment has been achieved, a sampling point can be selected to capture incoming data. The remaining portion of the training sequence is used correlate the recovered data to the proper "known" word alignment.
Figure 3: Basic variable digital delay line with N taps. A key design point for a de-skewing operation is that both the inverter cells and the gates used to implement the N:1 mux must have "balanced" rise and fall times.
Comparing the Two Approaches
As demonstrated above, in the areas of noise management, power usage, area, process sensitivity, testability, and skew management, a digital design offers superior and more efficient performance over an analog design for high-speed SerDes products. While some designers prefer to stick with the more traditional analog approach (due to reasons of comfort or risk aversion), many others are finding the advantages of the digital approach too compelling to ignore. And as the market demands for additional gains in speed, efficiency and/or price become louder, the argument for digital design becomes more and more persuasive.
About the Authors
Hansel Collins is Co-Founder and Chief Science Officer of TriCN. A graduate of Boston University with an M.S. in Computer Engineering, Hansel is responsible for development of TriDL, TriCN's all digital SerDes technology. Previous to TriCN, Hansel worked at Digital Equipment Corporation, where he specialized in memory subsystem design, clock distribution and de-skewing from which he obtained 8 patents for his efforts. He worked at Silicon Graphics as a system signal integrity engineer on the Origin 2000 systems project and invented the DSC Circuitry for the HIPPI-6400-PH standard.
Steve McConnell, vice president, marketing, joined TriCN is 2001. He is responsible for both marketing and business strategy, including creation of the TriCN business plan which lead to the successful funding of the company in 2002. An MBA graduate of the Haas School at UC Berkeley, Steve's background includes executive-level positions with Phoenix Pop Productions, 300FeetOut, and Publicis Technology.
Published with permission from the Fabless Semiconductor Forum's Quarterly Fabless Forum in June 2003.
For more information about multi-gigabit SerDes, visit TriCN's Web site