Today's embedded applications target the PC architecture that users have accepted beyond anyone's wildest dreams for both business and personal use. This is a wide-open target, supported by a vast range of hardware, software, development tools, and expertise. However, the competition is fierce. Provided that embedded applications are low-cost and with quick time-to-market, they compete based on how well they package their innovations and new technologies to optimize the user experience.
Optimizing user experience must take into account ease-of-use; otherwise, the consumer may decide in favor of an application that is not quite as impressive but that is more accessible. Improving embedded ease-of-use starts with removing legacy features that slow down the system and stand in the way of the progress made by newer platform technologies.
Letting Go of Legacy
The industry defines a legacy feature as one for which there is a faster, superior, easier, and/or less expensive alternative available. A good example of a legacy feature is the ISA bus, which for some time has remained part of embedded platforms despite the existence of buses that provide superior connectivity, such as Peripheral Component Interconnection (PCI), AC-97, and Universal Serial Bus (USB) interfaces.
The ISA bus has some very serious limitations. Even with expansion slots, it is incapable of supporting current-generation I/O requirements, which have evolved from 8/16-bit ISA bus access to 32/64-bit PCI bus access. Super I/O functionality has migrated to the LPC bus in anticipation of ISA removal. In addition, many functions such as audio, LAN, and IDE require more functionality and bandwidth than the ISA bus is capable of providing. The move to other buses has been a slow process, but one that has just about made the ISA bus obsolete.
Taking Over Where ISA Leaves Off
Intel introduced the LPC specification in 1998. The LPC bus standard provides a local bus on a platform with no device sockets, resulting in savings for both manufacturer and customer. Intel's standard consists of a minimum of seven signals and a clock speed of 33 MHz. You do not need any software modifications to enable migration to the LPC bus from the ISA bus. This is a big and unusual advantage, since most hardware changes require software modification. Legacy I/O peripherals that used the ISA bus, such as the mouse, keyboard, floppy disk drive, infrared, and parallel ports, are supported by a companion Super I/O circuit. This circuit has also migrated from the ISA bus to the LPC bus, improving system integration. Intel has also developed a new BIOS chip, called a Firmware Hub (FWH) that supports the LPC bus to replace the traditional BIOS chip that uses the ISA bus.
An acknowledged trendsetter, Intel envisioned the following two-phase migration to a legacy-free ISA-less environment that would begin by using the LPC bus:
- The first phase was to move the legacy I/O peripherals to the LPC bus, while moving non-legacy functions, such as modems, to the USB port.
- The next phase was to remove ISA slots, thereby forcing the migration for expansion to larger-bandwidth PCI slots, to the USB port inside the box, and to the FireWire interface (IEEE 1394) outside the box. This change would make ISA slots optional.
The embedded industry's recent push toward more powerful, higher-bandwidth solutions has finally made this vision come true.
Among the components that have migrated to the LPC bus are Intel's 828xx chipset support platforms, National Semiconductor's new chipset 5535 support platforms, and Super I/O devices. The LPC Super I/O components require the same feature-set as traditional Super I/O components, and must be capable of supporting a keyboard and mouse controller, floppy-disk controller, and serial and parallel ports.
Enhanced Performance and Support
In many cases, the LPC interface exceeds the performance of legacy buses. For example, an I/O peripheral on the LPC bus, assuming that there are no wait states, delivers a data-read cycle of up to 2.56 Mbytes/sec, as shown in Table 1. This compares to the average ISA I/O read transfer rate of 2 Mbytes/sec with an 8 MHz clock, or to the EISA interface with an enhanced clock of 14 MHz, which can perform I/O read cycles up to 4 Mbytes/sec.
|I/O Read Cycle
CYCTYPE + DIR
|Access Time (s)
Table 1: LPC Bus Performance for I/O Data-Read Cycle
The LPC bus is able to support wake-up and other power-state transitions, which the ISA bus cannot support. This increases the range of devices that can connect to the LPC bus, such as:
- Generic memory devicesLPC support for memory cycles
- Super I/O, audio, and system-management controllersLPC support for I/O cycles, DMA, and bus master.
In addition, the LPC interface supports:
- LPC DMA Request
- LPC Serial Interrupt Request
- Intel's Firmware Hub (FWH) BIOS chip for the LPC bus
- X-Bus data cycles, including memory, I/O, DMA, and data-bus master.
Board Design Benefits
Board designs that migrate to the LPC bus can derive numerous benefits, including:
- Significant savings in motherboard space, due to the removal of components and connectors. The motherboard form factor itself can be smaller.
- Higher integration of motherboard functions by reclaiming board space to provide additional ease-of-use benefits.
- Reduction of the +5, +12, and -12 VDC system power supply requirements as a result of ISA slot removal. The reduction is an estimated 15W per slot. Actual power savings are proportional to the number of ISA slots removed.
- Elimination of the -5 VDC, since ISA slots are the only system resources that require this voltage.
- Reduction of the chassis size, as a result of ISA slot elimination. This also allows for more optimal placement of internal peripherals.
- Streamlined BIOS code, due to the removal of ISA plug and play support.
Migrating to the LPC bus from the legacy ISA bus also carries with it performance and cost-related system benefits, such as:
- Alleviating legacy-related bottlenecks in memory management and performance
- Reducing manufacturing and software support costs
- Extending the reach of the application to a greater variety of embedded platforms by enabling increased flexibility in form factors.
Flash Storage Alternatives
When Intel designed the LPC bus, it named flash devices as the memory storage media that would be used on embedded platforms. Intel intended that flash would store system BIOS code and, on highly embedded applications, an EEPROM or another flash device would store OS images or software applications. Intel clearly understood the advantages of using flash-memory technology, largely based on the memory's physical structure. Flash technology is a solid-state, non-volatile technology that uses no moving parts to enable code and data storage. It consumes very little power and takes up limited space compared to alternative memory solutions.
There are two general categories of flash media: local (or embedded) and removable. To date, only local flash can interface to the LPC bus.
Three local flash storage alternatives are currently available for the LPC bus to answer different data- and code-storage needs:
- High-capacity data storage, up to 128 Mbytes, and code storage using a single device based on NAND technology
- Code storage only, from 0.5 Mbyte up to 1 Mbyte, using a single device based on NOR technology
- Highest capacity data storage and code storage, using three devices: an EEPROM for data storage, a Super I/O device to enable LPC integration, and a NOR-based flash device for code storage in capacities ranging from 0.5 Mbyte to 1 Mbyte. This alternative is costly in terms of real estate, Bill of Materials (BOM), and programming.
The first alternative is the most attractive in applications requiring both data and code storage, and when minimal space and lower costs are an issue.
Case Study: National Semiconductor's Thin-Client Platform with DiskOnChip
Traditionally, M-Systems' DiskOnChip products have supported the ISA bus on several thousand embedded platforms, such as National Semiconductor's thin-client platforms (Figure 1).
These products use NAND flash technology, optimized by manufacturers such as Toshiba and Samsung, for data storage operations. NAND flash performs write/erase operations over 15 times faster than NOR-based flash alternatives. NAND solutions also have an increased ability to withstand rigorous write/erase cycles over long periods of time. DiskOnChip products have a flash file system that enables the flash drive to emulate a hard drive, making it completely transparent to the operating system. Many DiskOnChip products can also store code to perform CPU initialization, platform initialization, or OS boot operations.
But NAND flash is an imperfect storage media that requires bad-block management, along with error detection and correction code to ensure data integrity. Technology within DiskOnChip manages the media to distinguish bad blocks from usable blocks. Based on Reed-Solomon error detection and correction algorithms, the technology uses hardware-based error detection for speed and efficiency, and software-based error correction to ensure data integrity.
For M-Systems, providing local storage targeted to the LPC bus, while incorporating all the advantages of its DiskOnChip products, has a definite advantage. Embedded designers can achieve flash disk data storage up to 128 Mbytes and code storage in one device, without using sub-ISA interfaces or ISA-based Super I/O devices. This technology also provides capacities high enough to store OS or software applications ported to the LPC bus. This eliminates the need for an expensive IDE port or for an additional removable data-storage device that occupies an IDE port on the platform.
Figure 2: DiskOnChip with an LPC interface in National Semiconductor's Geode-Based, LPC Bus Architecture
Figure 2 shows National Semiconductor's newest thin-client architecture that gives the user the option to choose between local storage using the LPC bus and removable storage using the IDE port.
About the Author
Sharon Dagan has been with M-Systems for two years, currently holding the positions of Senior Technical Marketing Engineer and Accessories Product Manager in M-Systems DiskOnChip business unit. Dagan manages the development of strategic partnerships in M-Systems target markets and also helps the company in defining new DiskOnChip accessories. From 1998 to 2000, Dagan worked for Lucent Technology in the Wireless Network group. He received a B.Sc. in software engineering from Tel Aviv University, and a B.A. in political science from the Hebrew University in Jerusalem.