The successful development of SoC products in the sub 90nm processes requires vewry close collaboration among a number of partners in different segments of the electronic industry. In particular, foundries and EDA vendors must work together to develop, document, and support a methodology that will guarantee a profitable yield level for chips designed with the methodology. The agreement announced today between Mentor graphics Corporation and Freescale Semiconductor is an example of such collaboration.
Mentor plans to provide EDA tools in several focused areas of the nanometer chip design flow. The plan includes tools in the areas of Design for Test (DFT), physical verification and analysis, advanced Resolution Enhancement Technologies (RET) and post-tapeout Design for Manufacturing (DFM). The new arrangement expands on an existing collaboration in areas where Freescale and Mentor can develop methods to improve test and manufacturing capability. Ross Hirschi, Director of Methodologies and Flow Development at Freescale said that his company aims to provide Manufacture-Aware Design methods at every phase of the chip design process, from architectural design to mask preparation.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.