Venice, FL — On March 28th both Cadence and Synopsys have announced additions to their support of the two competing low-power standards subject of much discussion and controversy in recent months. Taiwan Semiconductor Manufacturing Company announced the availability of 65-nanometer, low-power libraries from TSMC supporting the Common Power Format (CPF) recently released by the Low Power Coalition under the Si2 consortium. Cadence also announced that it has extended its existing TSMC library distribution agreement to include these libraries.
TSMC is a founding member of the Power Forward Initiative and has collaborated with Cadence on a number of low-power proof-point projects going back to 2003, including the most recent validation of CPF-based design technologies using TSMC's 65-nanometer libraries.
Cadence and TSMC have worked closely on low-power techniques since 2003," said Jan Willis, senior vice president, Industry Alliances at Cadence "The CPF-enabled design flow that we have proven through our collaborative work delivers the productivity necessary to accelerate the adoption of advanced low-power design techniques."
Although Synopsys, Inc. announcement was dated March 29, it became available on Yahoo Finance web site the previous day. In it the company announced that it is enhancing its comprehensive low-power verification and implementation solution to ensure compliance with the widely supported Unified Power Format (UPF) 1.0 Accellera standard. The enhanced solution with support for UPF 1.0 is expected to be available in the second half of 2007.
UPF 1.0 was created in response to customer demand for a standard that enables consistent and interoperable end-user low-power flows and methodologies. Built upon proven technologies donated to Accellera by key players in the electronic design automation (EDA) and low-power semiconductor markets, UPF delivers productivity gains and simplification of low-power design flows.
The format and technology have been proven by over 20 successful multi-voltage tapeouts that used Synopsys technology, parts of which are now incorporated into the Accellera UPF standard. The Synopsys solution spans the entire low-power design flow from hardware/software power trade-off at the system level through simulation and static verification of low-power intent, complete low-power RTL-to-GDSII implementation and sign-off, and a comprehensive set of low-power intellectual property (IP).
The DiscoveryTMVerification Platform enables power-aware simulation, formal equivalence checking, and static analysis of designs that use modern low-power techniques including multiple power domains, level shifters, isolation cells, and retention memory elements.
The GalaxyTM Design Platform includes advanced low-power techniques, such as multi-voltage and MTCMOS power gating, as well as more commonly used techniques such as clock gating and multi-threshold libraries. In addition, it performs comprehensive dynamic and leakage power optimization and analysis throughout the synthesis, physical design and sign-off phases of the design process.
Synopsys DesignWare® IP is architected for low power consumption in both active and standby modes. This is achieved by using power-efficient transmitters, phase-locked loop (PLL) blocks and clock gating techniques.
"Increasing our customers' market competitiveness has been a key driver for us in developing our low-power solution," said John Chilton, senior vice president of Marketing and Business Development at Synopsys. "Our Galaxy Design and Discovery Verification Platforms, complemented by a portfolio of low-power IP, offer our customers the comprehensive and advanced solution they need to quickly bring to market the most competitive low-power designs."