PARIS Taiwan chip maker Mediatek Inc. announced it has selected Edxact's Jivaro netlist reduction platform for analog circuits.
Mediatek said it will use Edxact's Jivaro tool to verify its analog circuit design flow.
The Taiwan-based company specified that it has assessed Jivaro on different designs and acknowledged the reduction capabilities achieved while maintaining accuracy. Simulations were faster.
Jivaro is a tool for the IC nanometer designs dedicated to the reduction of parasitic networks. It helps backend physical verification teams to reduce time to market by enabling and speeding up post layout simulation of huge parasitic extracted circuits, while keeping a very high accuracy, Edxact (Grenoble, France) noted.
Jivaro is claimed to dramatically accelerate IC simulation while preserving an outstanding accuracy and has already been adopted at leading IDM companies worldwide.