Solido Design Automation has signed an agreement with UK based Sipeda Ltd to act as its European representative. Solido develops EDA tools to compensate for process variations in analog/mixed-signal, custom digital and memory integrated circuits. It's a return to Europe in one sense, as Solido's know-how has been founded on a series of algorithms that were developed at Leuven University in Belgium by Trent McConaghy, Solido's co-founder and chief scientific officer.
"Solido is on the forefront of providing technology that addresses process variation challenges in transistor-level design," said Ian Yates, ceo of Sipeda Ltd. "The combination of our sales, consulting and business development services with Solido's technology will give European customers an unparalleled solution for their IC design needs."
Solido's core product is SolidoSTAT, a statistical tool for use by transistor-level designers to analyse and fix design failures caused by process variation. It is typically used for 90nm processes and below. Explains Amit Gupta, ceo of Solido: "Designers aren't realising the benefits of shrinking to smaller geometries. The tendency is to over-design to compensate for yield loss, by guard banding or adding more protection, leading to area bloat out and increased power consumption. Or, there is a risk of under-designing a chip, leading to what we have found can be anywhere from a 10 and 85% yield loss."
Explaining where SolidoSTAT fits in a typical design flow, Gupta says: "To understand the effects of process variation, our algorithms mine data from the simulation database. So we are integrated with Cadence's Spectre and Sypnosys' H Spice tools, among others. It's an additive tool into the designer's current flow." Acknowledging that the speed of simulation needs to be addressed, he adds: "Our algorithms achieve the speed of design that you would get with process-corner analysis and the accuracy of Monte Carlo analysis. As designers gain confidence in our tool, it could enable them to cut out the process corner step."
Whilst Solido's initial proposition deals with statistical effects, it is developing tools to deal with well proximity effects and stress effects, typically encountered at 45nm processes and below.
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