Targeting analog, mixed-signal, memory, and high-speed I/O designs, Apache Design Solutions has released Totem, an integrated power and noise integrity chip design platform that incorporates transistor-level noise injection, parasitics extraction, package modeling, dynamic analysis, and design debug in a single-flow. In particular, Apache claims that it addresses the challenges associated with global couplings of power/ground noise, substrate noise, and package/PCB capacitive and inductive noise.
Totem's key technology is based on the concurrent analysis of noise propagation through the power delivery network, substrate network, and package/PCB parasitics. It analyses noise-coupling effects at every time-point using a single-kernel solver - noise-coupling is a critical challenge for post submicron mixed-signal SoCs. The accuracy of power noise analysis, says Apache, is critical for functionality, timing, and reliability of analog designs.
Among the reasons Apache highlights for increasing amounts of noise injection are increased power density and higher speed of digital components. Also, limited die space is impacting the effectiveness of the guard-ring structure for analog macros. Totem's Substrate Noise (SE) technology includes extraction of the substrate network for advanced process technologies such as triple wells and various guard-ring structures. It also provides concurrent time-domain simulation of the substrate network, power/ground mesh, and package parasitics. Apache says that SE accounts for full-chip SoC substrate noise effect by interfacing with RedHawk, Apache's power integrity solution, to obtain the accurate substrate injection signature of all digital components.
Totem integrates with existing analog environments, allowing users to cross-probe their results with other industry standard circuit design tools. Apache suggests that designers can use Totem to guide their power network and package design during early stage prototyping, but also for chip sign-off and post-silicon debug. For example, Totem offers simulation-based electro-migration (EM) validation for power and signal nets, and supports Root Mean Square and Peak current EM checks, which are necessary when dealing with advanced process nodes. Totem also incorporates a transistor-level power model with voltage de-rated switching current technique, and SPICE-accurate decoupling capacitance extraction. Impact of package and board effects is included through the support of broadband S-parameter package and PCB models.
For more information, visit Apache's website