Winchester, UK - Renesas Technology Corp., has upgraded to the latest version of Cadence Virtuoso technology at its global design centers.
Renesas anticipates the constraint-driven design and verification capabilities in Virtuoso IC 6.1 will shave up to 30 percent off the turnaround time for its mixed-signal and analog designs while maintaining their high quality standards.
"Through our extensive evaluation, we now have confidence that Virtuoso IC 6.1 significantly shortens design turnaround time and brings us unparalleled productivity gains in our analog/mixed-signal designs," said Takao Sato, department manager, SIP & Analog EDA Technology Development Dept. in the Design Technology Div. at Renesas Technology Corp. "We have used Virtuoso technology for analog and mixed-signal designs for years and expect great results with our deployment of Virtuoso IC 6.1 at our worldwide design sites."
The constraint-driven methodology enabled by Virtuoso IC 6.1 technology can ease the way for IP reuse, while its constraint-driven verification capability can cut the time needed to ensure design intent is maintained.
Renesas cited the Virtuoso technology's advanced automation, including its yield optimization, parasitic-aware design mode and constraint template features as being extremely useful. Renesas engineers are using the constraint template to develop complex constraints for layout automation. The company's use of SKILL-based process design kits (PDKs) allows for more complex Pcells and faster design time with high-quality results.