Winchester, UK - Backend verification specialist, EdXact SA (Grenoble, France) and MediaTek Inc., (Hsin-Chu, Taiwan), a fabless semiconductor company for wireless communications and digital multimedia solutions, have entered a strategic relationship to deploy EdXact's netlist reduction platform for analog circuits.
"At MediaTek we will integrate Jivaro into our current design flows for our analog circuits in deep sub-micron processes. After verifying the tool on different designs, we were impressed by the reduction capabilities achieved while maintaining accuracy", said a representative of MediaTek's Design team. "With Jivaro we can carry out more simulations faster, which in return assures a high level of quality for our products."
"We are delighted to be chosen by MediaTek", said Mathias Silvant, President and Chief Executive Officer of EdXact. "In a very short time, MediaTek has become one of the most important developers of integrated circuits for mobile applications, mainly for the Chinese market. MediaTek's choice demonstrates the economical value of our technology for the development of low-cost, but high-quality devices."
The Jivaro model order based technology claims to be the only independent industrial netlist reduction technology available, which applies on post-layout extracted netlists. Jivaro remodels and reduces the parasitic overhead in a way that the simulation tool in place is able to simulate larger netlists, or reduce the memory footprint and the execution time.