PARIS On the eve of the 47th edition of the Design Automation Conference in Anaheim, Calif., Atrenta Inc. and AutoESL announced they will be demonstrating a working 3D design flow.
Resulting from an ongoing collaboration between Atrenta, AutoESL, IMEC and Qualcomm, the design flow is presented as the early version of a working system that addresses 3D-aware high-level synthesis, early partitioning, floorplanning and multi-domain analysis.
During the demonstration, partners said they will give an early peek into the future of 3D design, and Riko Radojcic, principal engineer and manager at Qualcomm, will discuss Qualcomm's development of the 3D PathFinding technology that supports virtual chip design for co-optimization of system design and 3D interconnect-packaging technology.
Radojcic said he will present the focus and goals of the PathFinding flow.
“Qualcomm has been developing a vision for a design system to address the needs of 3D for several years,” stated Radojcic. “We are delighted to see our vision, PathFinding, moving closer to reality through this collaboration.”