SAN JOSE, Calif. -- As expected, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has rolled out two reference flows to speed up new designs in the foundries.
The company introduced its so-called reference flow 11.0 and analog/mixed signal (AMS) reference flow 1.0. AMS claims to be the foundry industry's first analog/mixed-signal design flow. Both flows are key components of TSMC's Open Innovation Platform.
The reference flow 11.0 adds new features to its previously-announced 10.0 version. Both 10.0 and 11.0 are designed for its 28-nm digital process.
Reference flow 11.0 focuses on Electronic System Level (ESL) design, an SoC Interconnect Fabric, and 2-D and 3-D integrated circuits (2-D/3-D ICs) using through silicon via (TSV) technology.
AMS reference flow 1.0 is geared for TSMC's 40- and 28-nm process nodes. It includes a layout-dependent effect (LDE) aware design methodology and TSMC-specific LDE engine, complete DFM-aware analog layout guideline and checker utility, advanced analog base cell (ABC) design, and a design configuration management environment, all integrated on top of 28-nm interoperable process design kit (iPDK) and OpenAccess database.
The TSMC AMS Reference Flow 1.0 is developed and validated in collaboration with multiple EDA partners including Apache Design Solutions, Berkeley Design Automation, Cadence, Ciranova, EdXact, Magma Design Automation, Mentor, Pyxis Technology, Silicon Frontline, Solido Design Automation, and Synopsys.