SAN FRANCISCOSouth Korea's Samsung Electronics Co. Ltd. said its foundry business has qualified a 32-nm low-power process with high-k metal gate technology. The company lays claim to being the first foundry to qualify a low-power process using high-k at 32-nm.
Samsung (Seoul, South Korea) said the process has completed reliability testing at Samsung Foundry’s 300-mm logic fabrication line in Giheung, South Korea and, is now ready for production of customer designs.
Samsung will begin shipping wafers built using the process sometime next year, according to Stephen Woo, executive vice president and general manager of System LSI at Samsung. "Hopefully early in the year."
Most leading-edge chip makers had hoped to be using high-k dielectrics prior to now, but most have been unable to implement what has proven to be a difficult technology. The exception is Intel Corp., which has shipped 45- and 32-nm processors based on its gate-last, high-k technology.
Taiwan Semiconductor Manufacturing Co. Ltd., the market leader in silicon foundry, is expected to introduce a high-performance high-k metal gate process at the end of September. By December, TSMC hopes to have available a high-performance/low-power 28-nm process with high-k metal gate.
Samsung said the 32-nm, low-power high-k process was developed in conjunction with other members of IBM's so-called "fab club," the IBM Joint Development Alliance. Though the technology was developed in collaboration, Woo said Samsung has taken the lead in commercializing the technology. He noted that fab club member GlobalFoundries has stated its intention to skip the 32-nm node and move directly to 28-nm. Woo said he could not speak for IBM, but added, "This is a very important accomplishment for IBM as well from a technology perspective."
As expected, Samsung's first high-k offering is a "gate-first" process. There are two basic approaches to the next-generation gate stack in logic designs. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. In a gate-last approach, used by Intel, the gate stack is formed after source and drain.
Earlier this year sources told EE Times that Samsung was exploring gate-last technology as an alternative in high-k dielectrics.
Woo said Samsung is committed to using gate-first technology for HKMG at the 32- and 28-nm nodes, but that beyond that it is open to either possibility.
"What will happen beyond 28-nm requires more research and another debate," Woo said. "Samsung and IBM have an open mind on that. We will choose the best solution for our customers."
Ana Hunter, vice president of foundry services for Samsung, said semiconductor manufacturers tend to be a conservative group and that gate-first technology was considered the most simple implementation of high-k metal gate. "We feel that our implementation with gate-first has its advantage," Hunter said. "There have been significant changes in the materials, and we don't want to downplay that, but it gives us very significant advantages in gate leakage of more than 100X."