SAN JOSE, Calif. -- Looking to gain an edge in next-generation technology--reportedly including 3-D chips-- Qualcomm Inc. has joined chip-making consortium Sematech.
As the first fabless chip manufacturer to join Sematech, Qualcomm (San Diego) plans to participate in a ''high-level engagement'' with the group. Sematech and the cell-phone chip maker said they are looking to ''assess the feasibility of technologies that are designed to extend Moore’s Law.''
“Qualcomm has a long history of working with various industry partners to specify and drive the next generations of process technology,” said Jim Clifford, senior vice president and general manager of Qualcomm CDMA Technologies, in a statement.
For example, to accelerate its 3-D integration efforts, Qualcomm recently joined in a collaborative effort led by Leuven, Belgium-based IMEC, Europe's nanoelectronics research institute. Qualcomm was the first fabless semiconductor design company to join IMEC's 3-D integration program in 2007.
Rival Sematech also wants to expand its wings. The chip-making consortium is looking at ways to bring fabless companies into the fold and is also hoping to expand its collaborative efforts with fab tool makers, according to the new president and chief executive of Sematech (Albany, N.Y.). Until now, Sematech's members have been integrated device manufacturers (IDMs).
Qualcomm also may be looking for help in the development of 3-D devices based on through-silicon vias (TSVs). Sematech has a major program in the arena.
On Qualcomm's Web site, Clifford said he envisions TSV technology, ''allowing Qualcomm engineers in the not-too-distant future to achieve performance that is currently only a dream by combining modem, power-management and radio-frequency chips with just the right amounts of memory.''
Sematech's 3D program was established at CNSE’s Albany NanoTech Complex to deliver 300-mm equipment and process technology solutions for high-volume TSV manufacturing. Sematech has been working jointly with chip makers, equipment and materials suppliers, and assembly and packaging service companies on early development challenges for TSV, including cost modeling, technology option narrowing, and technology development and benchmarking.
Sematech recently reported advances in wafer-to-wafer bonding alignment accuracies through a series of tool and process hardening improvements. Wafer-to-wafer alignment and bonding are key enabling process steps for 3-D interconnection of wafers through stacking.
''Sematech has demonstrated submicron alignment accuracies for copper-to-copper (Cu-Cu) thermo-compression bonds and a variety of silicon-to-silicon and oxide-to-oxide fusion bonds without sacrificing bonding uniformity and bonding strength, using an integrated 300 mm (wafer-to-wafer) pre-processing, aligning, and bonding tool. Additional related metrology development on bonding interface defectivity and overlay metrology were also reported,'' according to Sematech.
At the recent International Interconnect Technology Conference (IITC), some experts came to the same conclusion about 3-D chips based on TSVs: It's not ready for prime time.
A plethora of companies, including ASE, Elpida, IBM, Intel, Qualcomm, Samsung, Toshiba, TSMC and others, are exploring the possibly of stacking current devices in a 3-D configuration.
Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying TSVs. The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.
So far, chip makers are shipping limited 3-D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers.
There are several problems with TSV technology: Lack of EDA design tools; complexity of designs; integration of assembly and test; cost; and lack of standards.