SAN JOSE, Calif. -- At the 2010 Symposium on VLSI Circuits in Hawaii this week, Intel Corp. will provide an update on its ongoing research on floating-body cells (FBCs) for advanced cache designs in microprocessors.
In a paper, Intel describes what it calls an FBC utilizing ''silicon on replacement insulator’’ (SRI) technology on a bulk substrate.
For years, FBC has been touted as an alternative to conventional cache memory. Current capacitor-based cache memory technology is running out of gas. FBC is a candidate for increased memory density, compared to the standard six transistor (6T) cache memory that is used on all microprocessors today.
In 2008, Intel described the world's smallest FBC-based planar device on silicon-on-insulator (SOI) technology for possible use at the 15-nm node. At the time, the big question is whether Intel is finally endorsing SOI technology. SRI also appears to be a form of SOI.
Intel has not implemented SOI-based FBCs in processor designs--yet. And it has yet to endorse SOI in volume manufacturing for processor designs. For years, Intel has dismissed SOI technology. Still, it is looking at SOI--at least in R&D.
At this year’s event, Intel updated its FBC efforts in two papers. In the first paper, ''A 15-nm node floating body cell (FBC) memory was demonstrated utilizing SRI technology on bulk substrate,’’ according to the paper.
''Planar floating body cell requires custom thin SOI,''
the presentation said. ''Alternative is to create a local SOI where needed, demonstrated on (a) realistic memory array.''
To build the FBC, Intel used a highly-selective, SiGe-based etch step and nano-scale anchors. This ''enabled the fabrication of silicon on thin replacement oxide of 12-nm,'' according to Intel.
''The memory characteristics show a memory signal of 7-microAmps and disturb retention time of 20-ms for a 51-nm gate length and 77-nm width device. This is the best FBC memory performance reported on bulk substrate,’’ according to Intel.
In the second paper, Intel describes a FBC memory fabricated on 25-nm undoped silicon as well 10-nm BOX SOI substrates--based on a new back-gate doping process.
''Back-gate doping process is revealed to be a critical part of the FBC integration. Back-gate dopant loss due to oxidation and high-temperature processes is minimized to enable high performance at scaled diffusion widths,’’ according to Intel.
The ''memory retention of over 1 second (@ 3-microAmps sensing window) in scaled cells (Lg=50 nm, W=85 nm) is suitable for 15-nm node,’’ according to Intel.