SAN JOSE, Calif. -- At this week's 2010 Symposium on VLSI Circuits in Hawaii, Intel Corp. will provide an update on its ''tera-scale'' processor R&D efforts.
Late last year, Intel demonstrated an experimental, 48-core processor--or "single-chip cloud computer"--based on a 45-nm process using high-k and metal-gate technology. The device is based on a ''two-core in a tile'' scheme and Intel Architecture (IA)--or x86-based--technology, instead of a previously-announced proprietary scheme.
In the future, Intel's so-called "single-chip cloud computer" or SCC processor could enable PCs to use "vision" to interact with people. Intel is now actively shipping the processor to research partners.
In a paper at VLSI, Intel will disclose that its SCC processor has a 40 percent improvement in terms of router-to-router latency in four clock cycles. Energy efficiency is 7.2 Tb/second per Watt. It operates at from 550mV-to-1.25V at 60-MHz to 2.35-GHz, according to Intel.
SCC is part of Intel’s so-called Many Integrated Core (MIC) architecture. The MIC architecture is derived from several Intel projects, including Intel's abandoned Larrabee graphics chip and such Intel Labs research projects as the 48-core SCC. The first MIC chip out the chute will be Knight's Corner, a 50-core chip designed in a 22-nm process.